Rx diversity becomes reality in HSDPA networks

The initial introduction of W-CDMA, in Release 99, provided three basic methods for delivering downlink data that included the dedicated channel (DCH), the forward access channel (FACH), and the downlink shared channel (DSCH). Since then, DSCH has been removed from the HSDPA specification because it was of little interest, and FACH is maintained for use with small packet information. DCH remains a key part of the data delivery system, running in parallel with HSDPA and offering a theoretical rate of 2Mbps with an in-field rate of 384Kbps (see Figure 1).



For HSDPA, there exists two extra downlink channels; the high-speed shared control channel (HSSCCH) and the highspeed downlink shared channel (HSDSCH). The HSSCCH has a fixed rate of 60Kbps and contains information such as the modulation scheme, data quality, various codes, and base station identifiers that the mobile application requires. The HSDSCH is the data channel and can support a theoretical maximum speed of 14.4Mbps (see Figure 1).



Release 99 and HSDPA have the same data format for the uplink with the only difference being HSDPA has an extra uplink channel called the high-speed dedicated physical control channel (HSDPCCH). The HSDPCCH is used to tell the base station the quality of the down link data.



The three new channels introduced in HSDPA, along with improved network scheduling, provide multiple advantages over basic W-CDMA, including:

• Higher downlink speeds;

• Adaptive modulation and coding schemes through controlled transmission parameters based on the radio conditions;

• Hybrid automatic-repeat-request (HARQ) for fast retransmissions of data containing numerous errors;

• Faster scheduling.RF REQUIREMENTS FOR HSDPA

Transmit requirements: Mobile W-CDMA terminals today have a maximum output power of either 24dBm (Class 3) or 21dBm (Class 4). Class 3 tolerance is defined to be +1/-3dB, allowing for a range of 21 to 25dBm, and Class 4 has a power tolerance of +2/-2dB, or 19 to 23dBm.



The extra HSDPA control uplink channel HSDPCCH operates in parallel with the normal W-CDMA dedicated physical uplink data (DPDCH) and control (DPCCH) channels. The HSDPCCH channel sets higher linearity requirements for the mobile transmitter since the peak to average ratio increases. The 3GPP specification allows the mobile application to lower its maximum output power for those time slots when HSDPCCH is transmitted. The allowable power reduction depends on the relative weighted powers of the uplink W-CDMA control ßc to the data ßd channel. If the power of the control ßc channel is lower than that of the data ßd channel, no power reduction is allowed in the standard. However, if the power of the data ßd channel is lower than that of the control ßc channel, the maximum power is relaxed by 2dB.



The quality of the output signal of the transmitter is characterized by an error vector magnitude (EVM). EVM is a measure of the error in a transmit signal due to impairments within the radio. The individual impairments consist of the carrier leaking out of the transmitter, distortion within the transmitter, errors in phase and amplitude, nonlinear elements, amplitude ripple and phase deviation from linear phase in pass-band, and noise (Figure 2).



The transmit output also has requirements on the amount of power it places in neighboring frequency channels. This is denoted as adjacent channel leakage ration (ACLR). The purpose of ACLR is to ensure protection of base station reception performance. The requirements for ACLR in HSDPA are specific since output power is relaxed depending on the control channel’s weighted powers. If there was no reduction in power allowed when the peak to average power increased, it would be difficult to maintain ACLR performance without redesigning the power amplifier. The ACLR requirements at 5MHz and 10MHz, offset from the carrier frequency, are -33dB and -43dB, respectively.



Receiver requirements: The sensitivity of a W-CDMA or HSDPA receiver is defined as the minimum power level where the receiver can detect data at a specific bit error level. The 3GPP specification requires that the receiver be able to detect a signal power level before the de-spreading of -117dBm. The sensitivity is defined for a 12.2Kbps voice transfer with a processing gain in the digital processor of 25dB, thus bringing the signal to -92dBm. The SNR required to detect this signal is 7dB. Therefore, the noise level has to be -99dBm (i.e. -92dBm minus 7dB). The noise at the input of the receiver is composed of two elements: 1) the thermal noise of the input signal itself and 2) noise leaking in from the transmit signal (see (Figure 2)). The thermal noise is given by the thermal noise floor of a 3.84MHz signal, which is equal to -108dBm. Assuming the thermal noise is predominant, the minimum noise figure required is 9dB (i.e. -99dBm minus -108dBm).



The receiver signal for HSDPA is either QPSK or 16-QAM modulated. For 16-QAM, the data is more susceptible to impairments such as DC offsets, errors in phase and amplitude, amplitude ripple and phase deviation from linear phase in pass-band, nonlinear element, and noise in the receive path, which affect the receiver EVM (Figure 2).



The use of receive diversity raised in connection with HSDPA has been incorporated in Category 6 utilizing a rake receiver with receive diversity, and in Category 7 using an equalized receiver with receive diversity. Diversity performance is a strong function of the actual antenna performance and the correlation between two antennae. Theoretically, diversity used in Category 6 HSDPA will increase the throughput by approximately 2.6 times.



A CMOS MULTI-BAND HEDGE TRANSCEIVER CHIP WITH RX DIVERSITY

CMOS processes are continually maturing in the area of RF design, making it the technology of choice in RFIC development because it is less expensive and more conducive to the large-scale integration needed for developing 3.5G mobile devices. To reap the full benefits of CMOS RF design a digital approach is needed, and by implementing digital-based transceiver architectures, RFIC designers can take full advantage of the switching characteristics of MOS transistors in CMOS, thereby significantly decreasing die size and current consumption.



Taking into consideration the functional natures of HSDPA and W-CDMA, along with both the transceiver and receiver requirements, an RFIC designer can implement receive diversity into a single-chip multi-band RF transceiver, thereby maximizing data throughput. Figure 3 demonstrates a single-chip multiband 3.5G CMOS RF HEDGE transceiver with on-chip receive diversity in a 7mm × 7mm × 1mm package design. With two distinct receive paths in its W-CDMA receiver the transceiver chip supports full receive diversity. When matched with a dual-antenna radio front end and a baseband processor that supports HSDPA category 9 receive diversity operation, it can enable downlink data rates up to 10.2Mbps throughout the cell.



ABOUT THE AUTHOR

Dr. Tajinder Manku is the chief technology officer and founder of Sirific Wireless. Dr. Manku has been awarded more than 30 patents at different stages and published more than 80 papers. Dr. Manku’s technical background includes solid state devices, IC design, and wireless system design. His academic background includes a B.S. in solid state physics and a PhD from the University of Waterloo. For more information, contact Sirific Wireless, 740 E. Campbell Rd., Ste. 300, Richardson, TX 75081; (519) 747-2292; www.sirific.com.