Power Math for improved power circuit energy efficiency

The use of the mathematical software package Maple offers an exciting and effective tool to study and understand physical phenomenon such as MOSFET switching in power circuits. In this article, we will examine the effects of the lumped and distributed gate resistance on the phenomenon of shoot through also known as cross conduction in synchronous buck converters (see Figure 1).



Lumped parameters models offer insight into the phenomenon and offer engineers a range of tools from the simple Ref. [1] to the more complex Ref. [2] to evaluate the susceptibility of a given synchronous rectifier for cross conduction in a synchronous buck converter.



Figure 2 depicts the complete lumped circuit for a synchronous rectifier including inter-electrode capacitances, resistances and source and gate inductances used for deriving the node equations to be solved for the shoot through voltages in this case.



Figure 3 shows simple model results in the lowest value of gate-source voltage during shoot through. The more complicated model adds both the parasitic gate and source inductances and clearly results in higher shoot through voltage.Finally, adding the inter-electrode resistors results in the largest shoot through voltage. It is worth mentioning that the gate-source voltage internal to the die is different from that between the external gate and source terminals on the device and the peak value is larger and takes place at a different time leading to the conclusion that simple external observations are not sufficient to determine whether cross conduction takes place or not when measured in the lab.

Figure 4 shows the current flowing in gate-drain capacitance, Cgd, and to a large extent in the gate driver for a drain-source rise time of 1ns. This large current, 16A, will add to the drain current of the control MOSFET and aggravate the dynamic losses situation.



In reality, all MOSFET parameters are distributed over the entire surface of the silicon device. This situation is namely one in which the equations that govern every cell on the device are different from any other cell. Hence, cross conduction will take place, and when it does, at different times and at varying magnitudes.



Figure 5 depicts the complete model of a synchronous rectifier (between dotted lines) used in the analysis with distributed gate resistance, Rg, gate-source capacitance, Cgs and Cgd. The equivalent circuit used in the mathematical analysis using Maple was done by dividing the die into 10 segments (S1...S10) with the assumption that each cell within a given segment has identical conditions of voltages and currents to each other cell. MOSFET segments S1...S10 represent the synchronous rectifier if it were sliced in 10 smaller sections with proportionately scaled parameters.



Using the above assumption, Figure 5 depicts the circuit used for the derivations of the voltages and current equations transform for the distributed parameter case. We assume that the 10 segments where cells in each segment has identical conditions. A set of 11 simultaneous differential equations were derived and solved using Maple. Figures 6 through 8 show the results in a 3D format that is easy to visualize and understand.



Figure 6. Drain current and gate-source voltage of one segment as a function of gate-source capacitance Cgd.

Assuming a step voltage at the drain of the MOSFET, Figure 6 shows the gate-source voltage of one segment of the synchronous rectifier, the gate threshold voltage plane and the drain current as a function of time and Cgd. The current starts conducting after the gate-source voltage level crosses the gate threshold voltage and spikes rapidly as the voltage increases.



Segment currents are not identical from one segment to the other and segments farthest away from the gate pad conduct the majority of the drain current while the drain current in the remaining segments represents a very small percent of the total device drain current. This leads to the conclusion that a small percentage of the die surface takes the majority of the shoot through power losses while the rest of the die may or may not have any shoot through whatsoever.



If the part of the die that is taking the majority of the power dissipation can withstand its thermal effects without overheating beyond 150C - 175C under the worst case conditions, then there is no harm done. As the rise time increases to achieve lower dynamic power dissipation, the cross conduction problem is likely to get worse unless the MOSFETs are designed in some innovative way to eliminate shoot through altogether. Only then, cross conduction could no more poise a challenge to the design engineer.



Figure 7 depicts the drain current and shoot through voltage of segment number10 as a function of the gate-source capacitance Cgs. Changes in Cgs has the largest influence on the on the drain current and consequently the shoot through losses.



Figure 8 Drain current and voltage of one segment as a function of RG

Figure 8 shows the effects of the gate ESR, Rg, on the drain current and the shoot through voltage.

While the influence of both Cgd and Cgs is limited in a very narrow window of typical values the effect of Rg is wide reaching along the entire range considered.



Conclusion: The use of the mathematical software package MapleTM allowed us to investigate the interaction of all the important parameter in a three dimensional representation, 3D, that helps understand the extent of the interdependencies. 3D graphing offers a very powerful visualisation tool of the complete results. To achieve the same results using any numerical simulation environment requires enormous amount of batch simulation, data compiling and graphing



References:

(1) Evaluating MOSFET Susceptibility for Cross-Conduction, Alan Elbanhawy, Fairchild Semiconductor, PCIM Magazine, Europe

(2) Shoot through analysis with parasitic inductance, Alan Elbanhawy, Fairchild Semiconductor, PCIM Europe Conference 2004