Companies that require semiconductor assembly may not have full understanding or the resources to consider all assembly aspects of a build. Companies can be compartmentalized in exclusively thinking about chip design without considering how it all comes together with packaging. This can lead to problems, as footprint and package constraints may not address the needs for the end design. Chip companies need to think about the final design even in the planning stages of chip design and determine the feasibility of thefinal form. The industry trends toward smaller designs while maintaining or exceeding performance of previous designs. Oftentimes, companies do not think beyond the initial design and do not realize that a collaborative feasibility is key to developing a successful end design solution. The design process must not only be focused on the IC level but also on the substrate level, and subsequently the PCB level. Understanding the packaging design process and the key considerations can help companies focus their package options and minimize the design phase. THERMAL PERFORMANCE If a package cannot meet the device thermal performance requirements, there is no need to move forward with package considerations. Based on three components (see Figure1)—power dissipation, ambient temperature, and maximum junction temperature—a general Theta-ja (degree C/W) value can be calculated to provide insight forthe package selection. Additional options to consider—such as air flow, thermal ballmatrix and exposed die attachedpads—will enable companies tonarrow down the options further. Additionally, several other factors can be implemented to confirm if a package can meet the design requirements. Increased substrate layer count, increasing copper plane thickness, adding heat sinks/ slugs, increasing the package size and direct thermal dissipation transfer can help the design see the light of day. NARROW DOWN CHOICES To understand substrate performance requirements, it is important to know specific performance requirements and capabilities of the substratetechnology. The design’s signal integrity parameters—such asclock speeds, signal impedance,differential signal routing,current requirements, cross-talkspecifications and signal parasiticparameters (RLCG)—are critical. Understanding the signal integrity needs and physical considerations—such as bond wire lengths/placement, reference plane requirements, maximizing signal path widths, minimizing the critical signal path lengths, and choice of plating technology—will benefit the electrical performance. Working closely with package characterization data (see Figure 2 ) will help guide and determine the proper substrate technology to meet the performance requirements. PHYSICAL SIZE AND CONNECTIVITY Based on the thermal and electrical assessment, the package technology options (FBGA, PBGA, QFN, etc.) are now clear. The remaining two considerations, physical size and connectivity, further narrow down the options until the ideal package and design scenario are developed. Typically, the basic physical package attributes are defined by the customer. Attributes such as desired lead/ball pitch, layer count, package thickness, and required lead or ball count are based on the PCB mating and the number of total I/O pins, as well as power and ground pins. Based on these inputs, the target package can be solidified if thermal and electrical performanceis not compromised. Once the package has been selected, the package connectivity can be investigated. The connectivity is the conductive path that includes the die, wire bond, BGA bond finger or leadframe lead. Understanding the manufacturability of the substrate vendor’s design features is essential. Critical design elements that are key to feasibility studies are the bond finger pitch, the finished bondable bond finger top flat width, the signal trace pitch as well as the drill type (mechanical or laser), and drill diameter with respect to the via pad diameter and substrate layer count. BRINGING IT TO THE MASSES If the package cannot be assembled in high quantities with high yields, the design will not be successful and it will force the assembled package to be reworked or redesigned. With this in mind, it is important to review the die pad layout as a part of the feasibility. Assembly sub-contractors publish inline and staggered die pad design rules that coincide with their wire bond machine capabilities and are based on their qualified process capabilities (see Figure 3 ). Knowing die pad pitch, die pad opening, corner pad spacing and staggered die pad row signal ordering requirements up-front can save valuable time and reduce wire length, wire angle, wire-towire clearance and wire crossingviolations. With the continued push to reduce package footprint and improve package performance, there is more to consider than just simple physical package parameters. The design feasibility process can be complex, with many issues to evaluate, but always starting with thermal performance. Electrical performance will narrow down package choices further, but only if package size and connectivity allow. Thorough planning in design package selection and evaluation will ensure optimum results and ultimately, success when the package goes to production. |
