IC power management requires a careful balancing act

As the electronics industry moves to new IC-fabrication technologies, chip designers must deal with tighter power specifications and with new power constraints. In large and complex designs, implementing a reliable power network and minimizing power loss have become major challenges for design teams.



Dynamic power dissipation occurs in logic gates as they switch states. During switching, power supplies must charge internal capacitance associated with a gate’s transistors. That process consumes power. The gate also must charge any external, or load, capacitances that comprise parasitic wire capacitances and input capacitances associated with downstream logic-gate inputs. The following equation (Equation 1) shows the relationship between dynamic power dissipation (Pd) and frequency (F), load capacitance (Cload), and supply voltage (V):





By minimizing circuit activity, reducing the supply voltage, or reducing the capacitance a gate must drive, IC designers can decrease the dynamic power dissipation for a semiconductor device. As designers reduce the frequency of a system's clock they reduce switching activity and minimizing circuit activity. They also can gate a clock signal and distribute it to only the portions of an IC that need the signal at a given time. And, by appropriately balancing delays, they can minimize local data activity, glitches, and hazards.



Designers can use two techniques to reduce capacitance. First, they can reduce the size of gate circuits, thus lowering their capacitances. Second, they can apply a power-aware placement algorithm to minimize the length of critical conductors, which thus reduces their parasitic capacitances.

By decreasing an IC's supply voltage, designers reduce a logic gate’s power consumption, but they also reduce the gate's switching speed. To overcome this speed decrease, designers can have different areas on a die run at different voltages. Key chip functions would operate at one voltage, while other circuits would run at a lower voltage.



STATIC POWER DISSIPATION

Static power dissipation occurs in inactive, or static, logic gates. Even though one static gate does not consume much power, total power consumption becomes significant because ICs now contain tens of millions of gates.



You must consider mathematical relationships when you address static power dissipation. Equation 2 describes the leakage current (I) associated with the transistors:





Here Vth equals the transistor’s threshold voltage and T equals temperature. Multiplying the leakage current (I) by the IC's operating voltage yields the static power dissipation. The equation above shows that static power dissipation has an exponential dependence on a transistor’s temperature. As a chip heats up, the static power dissipation of its transistors increases exponentially.



Equation 3 shows that lowering the supply voltage (V_dd) increases gate delays.





But, lowering the transistors’ switching-threshold voltage (V_th) speeds them up. As shown in Equation 2, though, increasing Vth exponentially increases the transistors' leakage current and their static power dissipation. (In Equation 3, K provides a proportionality constant for a specific fabrication technology and α relates to specific transistor characteristic.)





The results from Equations 2 and 3 show that IC designers must perform a complicated balancing act. Lowering the supply voltage reduces the amount of heat an IC generates, but it also increases gate delays. IC designers can choose to apply low-Vth transistors only in timing-critical paths and higher-Vth transistors elsewhere. And as explained earlier, they can use several supply voltages for different parts of a chip's circuitry.



POWER DISTRIBUTION

Of course, designers must get current from a power supply through a device’s pins and to the silicon chip. The wires that distribute power throughout the chip have resistance. The longer the wires, the larger the resistance and the greater the associated voltage drops and power losses. So, traditional packaging technologies based on power pads around the periphery of a chip no longer offer an acceptable option for large and complex devices.



Flip-chip packaging technology, though, places power pads across the “face” of an IC die and delivers power through short, low-resistance paths directly to internal areas on the chip. Thus a flip-chip can provide additional power and ground pads that reduce resistances and reduce power loss.



VOLTAGE DROP EFFECTS

Deep-submicron and ultra-deep-submicron devices are prone to voltage-drop effects. Such effects are caused by the resistance associated with the network of wires used to distribute power and ground from the external pins to the internal circuitry.



Voltage drop effects have become increasingly significant, because the resistivity of the power and ground conductors rises as chip-design geometries decrease. Increasing the width of power and ground "tracks" decreases resistance, but at the cost of valuable space of a silicon die. The wider tracks also may cause routing-congestion problems. To overcome this congestion, designers can place logic functions farther apart, but the longer signal tracks increase delays and power consumption.



IC designers must always balance the effects noted above to achieve an optimum power network for a specific design. In some cases, they may have some leeway, depending in circuit specifications, so perhaps their budget will let them specify a slightly larger IC die to achieve a commensurate power saving.



About the author

Arvind Narayanan is a product director at Magma Design Automation. He holds a Masters Degree in Electrical and Computer Engineering (Mississippi State University) and a Masters Degree in Business Administration (Duke University). He can be reached at arvindn@magma-da.com.