FRAM reaches highest capacity to date

Bridging the gap between the traditional mainstream semiconductor memory technologies of volatile RAM and non-volatile ROM, ferroelectric random access memory (FRAM) is continuing to grow in popularity among design engineers as the nonvolatile memory of choice. Following Ramtron’s recent commercial manufacturing agreement with Texas Instruments and the implementation of FRAM technology on TI’s proven advanced 130 nanometer CMOS manufacturing process, FRAM has surpassed the 1-megabit capacity limit, quadrupling its density to 4-megabits in a standalone memory device (FM22L16) that is already sampling. Full production quantities are planned for later this year and Ramtron is already developing follow-on products that are currently under test.









FRAM memory combines the fast access and low-power qualities of volatile RAM with the ability to retain data without power. Other non-volatile memories such as EEPROM and Flash are less efficient to embed because of multiple mask steps, longer write times, and increased power required to write data. FRAM also consumes much lower power than MRAM and is already commercially proven in demanding automotive, metering, industrial and computing applications.



More specifically, four distinct factors account for FRAM’s continued rise in popularity.



Firstly, unlike other non-volatile memories based on floating gate technology with long write delays, FRAM writes at bus speed. This means it performs write operations at the same speed as read operations, so no delays are needed for the write data to become non-volatile. This compares to a typical EEPROM, where a write operation can take 10 milliseconds to be effective after the data is written to the input buffer. Furthermore, there is no erase operation with FRAM since there is no preferred or default state. So, as with other RAM technologies such as SRAM, data is written without regard to the previous state.

Secondly, FRAM effectively offers unlimited write endurance. It doesn’t wear out like other non-volatile memory types. Floating gate devices, for example, stop retaining data when they have been erased too many times. This is a hard failure mechanism. A fatigued memory cell can no longer store the programmed state. FRAM does not exhibit this type of wear out.



Thirdly, FRAM operates without a charge pump, enabling low power consumption. Floating gate technologies require a high voltage to program a new state, which means that write operations consume considerably more power than read operations. In comparison, FRAM writes at the process core voltage, be it 5 volts, 3 volts or lower on more advanced processes.







Fourthly, as a RAM-based technology, FRAM lends itself well to both code execution and data storage but also offers the additional benefit of non-volatility, which means that data is retained even when no power is available. By serving as a potential single memory choice for both code and data, it overcomes the ongoing design dilemma of which memory type to implement. Invariably, design engineers have ended up implementing two types – one for code and one for data. Until now, however, the practical limit to using FRAM has been the available memory density, which has precluded its use in some applications, although this is fading fast following the agreement with TI.



HOW FRAM WORKS

So how does FRAM work? At the core of FRAM technology are tiny ferroelectric crystals integrated into a capacitor that allow FRAM devices to operate like fast non-volatile RAMs. The electric polarisation of the ferroelectric crystals is shifted between two stable states by the application of an electric field. The direction of this electric polarisation is sensed by internal circuits as either a high or a low logic state. Each orientation is stable and remains in place even after the electric field is removed, preserving the data within the memory without periodic refresh. The ferroelectric thin film is placed over CMOS base layers and sandwiched between two electrodes. Metal interconnect and passivation complete the process.



FRAM technology has been matured significantly since its inception. Initial FRAM devices required a two-transistor/two-capacitor (2T/2C) memory architecture, which resulted in relatively large cell sizes. Advances in ferroelectric materials and processing subsequently eliminated the need for an internal reference capacitor within every cell in the ferroelectric memory array. This one-transistor/one-capacitor cell architecture operated like a DRAM using a single capacitor as a common reference for each column in the memory array, effectively cutting the required cell area in half compared to existing 2T/2C architectures. This architecture significantly improved the die leverage and reduced manufacturing costs for resulting FRAM memory products.



FRAM has also migrated to smaller technology nodes to increase the cost effectiveness of the memory cells. A move to a 0.35-micron manufacturing process reduced the operating power and increased the die leverage per wafer compared to earlier generations of Ramtron’s FRAM products built on the company’s own 0.5-micron manufacturing line. By moving to TI’s 130nm process, the process limitations with regard to device densities inherent in FRAM devices has effectively been eliminated, establishing a new benchmark in the production of high density FRAM devices.



130NM PROCESS

To deliver the new 4-megabit FRAM, TI added only two additional mask steps to its standard, 130nm copper-interconnect process. The device uses the smallest commercial FRAM cells shown-to-date, measuring only 0.71µm˛, and enabling a higher memory density than that achieved with SRAM cells. To achieve this cell size, the process features an innovative capacitor-over-plug process that places the non-volatile capacitor stack directly on top of the W-plug transistor contact. The ferroelectric capacitor is formed using Iridium electrodes and a thin Lead Zirconate Titanate (PZT) ferroelectric layer.







TI inserts the nonvolatile memory capacitors above the contacts and below the first metal layer of their standard five level copper metal process. The 0.4µ2 capacitors are patterned using a single mask and a second mask makes the connection between the top electrode of the capacitor and metal. The two-mask adder compares very favourably with the 5-7 masks required by other memory technologies and makes FRAM an ideal solution for embedded non-volatile memory. The FRAM process insert has almost no impact on the underlying CMOS technology, thereby allowing full use of TI’s rich standard cell library.



According to Dr. Ted Moise, director of FRAM development at TI, the new process “achieves cost, power and performance standards that will be difficult for other non-volatile memory technologies to match.” Ramtron’s 4-Mbit FM22L16 parallel FRAM is the first device off the line. Designed to drop into 256Kb x 16 SRAM sockets, the x16 interface and ATD access mode provide a glueless interface with many microcontrollers, while separate upper/lower byte control allows simple integration with 8-bit systems. Available in a green 44L TSOP-II package, the FM22L16 is pin-compatible with 4-Mbit SRAMs. With a 110 ns cycle time, the FM22L16 is Ramtron’s fastest parallel memory. Its 4-word page mode allows the average cycle time to approach 55ns. As with all FRAM devices, writes occur at bus speed and are immediately non-volatile. Operating at full speed, the FM22L16 draws only 18mA. Standby current is typically 150µA and an ultra low current sleep mode reduces current draw to below 5µA, making the FM22L16 an attractive non-volatile memory for battery-operated systems.