One of the most critical factors in designing handheld, portable electronics today is reducing overall system power consumption. With increased consumer expectations, portable devices require longer battery life and higher performance. Even power reductions on the order of 10mW are crucial to portable system designers and manufacturers.
Several design techniques are used by designers to significantly reduce overall system power consumption, including, reducing operating voltage, optimizing system and CPU clock frequency, eliminating spikes of large current consumption during the power up sequence, efficiently managing system battery operation, efficiently managing operating mode of system devices, minimizing bus activity, reducing bus capacitance, and reducing switching noise.
One of the most important power saving techniques is the ability to manage the operating mode of devices in the system. Many manufacturers offer devices with power saving modes that temporarily suspend the device from its normal operation. These devices have the option to power down or transition to a non-functioning state if the device is not active for a specific amount of time. This feature is available on many of today’s microprocessors and microcontrollers. By taking advantage and managing the operating mode of large power consumers on a PCB, such as the processor, the overall power consumption of the system can be reduced significantly.
Reducing power consumption not only involves correct management of the operating mode of a device, but designing a system to take advantage of the modes a device can operate within. Off loading operations of the microprocessor allow it to stay in its low-power state for a longer amount of time. One way to reduce system power is to allow a low-power programmable logic device, such as a CPLD, to manage these off loaded operations. This article will describe this possibility along with types of operations that allow a processor to remain in low power state longer, thereby reducing system power consumption.
MICROPROCESSOR OPERATING MODES
In some portable applications, the CPU can consume 30 percent of the overall system power. Figure 1 illustrates the typical power consumption of system components in a Web Pad application.
Microprocessor power consumption can range from 720µW to 1W during normal operation. Microprocessor operating modes vary by part and manufacturer and include modes such as normal, run, sleep, suspend, standby, stop, and idle operation. Operating modes can vary in power consumption as much as 230mW between states. Normal operation of some low power microprocessors can be as little as 250mW.
EXAMPLE
Note: The microprocessor reference provided is an example to illustrate the power consumption in different operating modes. Since no standard method exists to determine power consumption, the data provided in this document is based on data provided by the manufacturer and is to be used for reference only. Please see "References" for more information.
To illustrate the difference in power consumption of operating modes in a microprocessor, an example is provided. Figure 2 illustrates the power consumption of the Intel StrongARM SA-1110 microprocessor operating modes. The power dissipation numbers shown in Figure 2 are determined by operating at 206 MHz with a nominal external voltage supply of 3.3V and internal voltage supply of 1.8V.
Operating modes of the StrongARM processor include normal, idle, and sleep. In normal operation, the CPU is full-on, with the device fully powered and receiving active clocks. In idle mode, even though power is applied to the CPU and other components, all clocks to the CPU are stopped, with only clocks to peripheral devices active. In sleep mode, power to the CPU and other peripheral components is disabled. Sleep mode disables all functions except the real-time clock, interrupt controller, power manager and general purpose I/O.
OPERATING MODE CONTROL
Microprocessors with power saving modes have an on-board power management controller. Operating modes allow the operating system or software application to temporarily suspend the CPU. The microprocessor executes a series of instructions to be placed into a power saving state. Once in a power down mode, several components of the microprocessor can still respond to system interrupts.
For example, the idle mode of the StrongARM SA-1110 processor saves significant power, but certain modules remain powered, such as the LCD, memory and I/O controllers. Even though the clock to the CPU is stopped, peripheral modules are still active. The Idle mode can still consume a significant amount of power, on the order of 100mW. By placing the processor into the Sleep mode, only active modules are powered to respond to interrupts and wake up signal requests. Sleep mode consumes even less power than Idle mode; current consumption can be less than 100mA.
For a microprocessor to return to normal operation from a power down mode, an event must occur. The following events can wake up the processor, but vary based on manufacturer, part and current operating mode:
Hardware reset
System interrupt
General purpose I/O interrupt
Real-time clock interrupt
OS timer interrupt
Peripheral interrupt
External wake-up signal
Upon recognition of an enabled wake up event, the microprocessor will begin a series of steps to wake up from a power down state. Figure 3 illustrates the general flow for a processor waking up from a power down mode.
CPLD DESIGN
Operating modes are used when the microprocessor is idle for a specific amount of time. When a microprocessor receives an enabled interrupt, the processor will respond to the interrupt request. When the processor is responding to the interrupt, it will operate in its run or normal mode. Reducing the number of interrupts to the processor will increase the time the processor is in a power saving state. Ideally, if the microprocessor does not have any instructions to execute, it will remain in a power saving mode forever. Inserting an external device to respond and handle system interrupts can reduce the operations required of the processor. By allowing the microprocessor to stay in its power down mode as long as possible, significant power savings can be realized.
Using a low power programmable logic device to supplement the microprocessor will save system power and increase system battery life. The industry’s latest CPLD offerings simultaneously deliver high performance and low power consumption. The standby current of a typical low power CPLD is less than 100µA. Figure 4 illustrates using a reprogrammable CPLD to interface to incoming system interrupts. Using an external data acquisition device to off-load interrupt requests required of the microprocessor will reduce overall system power.
SYSTEM INTERRUPTS
Depending on the end application for the processor, a variety of external devices may interrupt the processor. These interrupts include both data acquisition and data processing requests. By separating data processing interrupts to the microprocessor, data acquisition interrupts can now be serviced by the external CPLD. Using a CPLD to handle data acquisition interrupts will off-load interrupt requests to the microprocessor and save power.
Categorization of the type of data acquisition interrupts to the CPLD will depend on the end application. Peripheral devices or incoming data demanding a response to incoming data can be classified as data acquisition interrupt requests. Data acquisition interrupts include memory access interrupts; communication interfaces such as I2C, UART, SPI, or ISA, general-purpose I/O interrupts, and LCD interface interrupts.
These examples of interrupts that can be processed by the CPLD provide a starting point for the system design.
OPERATIONAL FLOW
Figure 5 illustrates the main operational flow for the design of a CPLD. Once a valid external interrupt is recognized by the CPLD, it will determine if it contains the functionality to process the interrupt. Once the CPLD has processed the interrupt, it can assert an interrupt to the processor for any data processing requests needed. If the CPLD is unable to process the interrupt, the interrupt is passed to the processor. The CPLD also monitors the operating state of the processor.
The low power CPLD design consists of an interrupt interface and controller to handle interrupt requests, the functionality to process the interrupt and a processor interface. The main functions of the CPLD will be described in more detail:
Interrupt interface. The interrupt interface of the CPLD receives all external device interrupt requests previously recognized by the microprocessor. The interrupt interface determines if the CPLD is capable of processing the interrupt request. The CPLD handles data acquisition interrupts that request data receiving and storage capabilities. If the CPLD is unable to process the interrupt, the interrupt is passed to the microprocessor. The CPLD interrupt interface provides the masking capability for all interrupt sources and the ability to determine the interrupt source. Programmable logic provides flexibility to change the trigger mode, which includes a high or low level and falling or rising edge sensitivity. The CPLD interrupt control registers are similar to the registers in the microprocessor.
Interrupt controller. The CPLD interrupt controller emulates the functionality that exists in the system microprocessor. The interrupt controller interprets from which device the data acquisition interrupt was received and initiates the processing of the interrupt. The CPLD processes the data acquisition interrupt request that would have otherwise interrupted the microprocessor. The interrupt controller initiates the action to process the request. An example of this is an application where the CPLD is receiving data from a remote device. The device is requesting to write the data being sent into memory. The CPLD interrupt controller recognizes a valid interrupt and initiates the memory interface to interpret the data.
Peripheral device interfaces. The CPLD provides the interface to system devices that are needed in processing interrupt requests. Device interfaces that are needed are dependent on the end application. When an external device interrupts the CPLD to read or write data into a memory component, that particular memory interface is needed in the CPLD design. The types of interfaces needed can range from memories to LCD interfaces to communication interfaces such as PCI, UART, SPI and ISA.
Microprocessor interrupt interface. The CPLD, like any external device requesting services of the processor, has the capability to interrupt the microprocessor. The CPLD must be able to interrupt the microprocessor once a data acquisition operation is complete. The designer has the option to set the priority level of interrupt requests from the CPLD and whether or not interrupts received from the CPLD will wake the processor from a power down state.
Microprocessor operating mode interface. Depending on the system microprocessor, the CPLD will be able to recognize the operation state of the processor. Some microprocessors provide external pins that represent the current operating mode. Depending on the CPLD and microprocessor design, the CPLD could recognize the current operating state of the processor and determine whether to assert an interrupt to the processor to execute a waiting interrupt. For example, if a low priority interrupt is received by the CPLD and the processor does not need to transition from its low power state, the CPLD can create a register indicating pending interrupts. Then when the processor wakes, the interrupt pending register can be read by the microprocessor.
BENEFITS
Figures 6 and 7 illustrate the power savings that may be realized in a typical battery operated device using a leading edge, low power CPLD (Figure 7) versus a stand alone microprocessor design (Figure 6). The power requirements of the CPLD are minimal compared to the power savings realized by keeping the microprocessor in its low power modes for a longer amount of time. Standby current of a typical low power CPLD is on the order of 100µA. The operating power consumption depends on the application and clock frequency. For a 64-macrocell CPLD fully populated with 16-bit counters and a 50MHz clock, ICC is approximately 10mA. Note that the actual power savings realized will depend on the system design including the type of microprocessor and the CPLD design.
Along with power savings attained using a CPLD, interrupt response time is reduced. The peripheral device no longer has to wait the delay time for the microprocessor to wake from a power saving state. Additional design savings can be realized and include reducing the number of interruptions to the processor; reducing the number of processor wake up cycles over a length of time; reduction of clock frequency without impact on throughput; running processor at lower frequency for data processing operations; and running the CPLD at a higher frequency for data acquisition operations.
CONCLUSION
Designing a power-sensitive application involves not only using software for power management, but utilization of hardware design techniques. Designing a low-power CPLD to keep a microprocessor in a low power operating state longer can significantly reduce system power consumption. The latest CPLDs on the market today offer a flexible combination of low power and high speed for any end application.
About the author
Mark Ng is an Applications Engineer at Xilinx, Inc. For more information, please contact Xilinx, 2100 Logic Dr., San Jose, CA 95124-3400; (408) 559-7778; www.xilinx.com.
References
Intel StrongARM SA-1110 Microprocessor Developer’s Manual. June 2000.
DragonBall Power Management. Motorola Semiconductor Application Note. Motorola, Inc. 1998.
Geode GX1 Processor Series Low Power Integrated x86 Solution. National Semiconductor. October 2000.
Turley, Jim. Microprocessors for Consumer Electronics, PDAs, and Communications.
Microprocessor Report. September 1999.
EDN Access. 27th Annual Microprocessor/Controller Report. Sept. 2000.
Click here for Illustrations:
Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7
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