Power management techniques for portable software defined radios

The design of a portable joint tactical radio system (JTRS) that must support a variety of waveforms should involve close consideration of processing performance and power utilization in this type of power-limited system. Integrated circuits with voltage and frequency scaling technologies offer the potential for a significant increase in battery life for handheld, manpack and portable software defined radios.



The JTRS is a Defense Department initiative to develop a family of software-programmable tactical radios for voice, data and video communications, as well as interoperability across the battlefield. There are four major domains: ground domain, airborne domain, network enterprise domain and special radios. These software defined radios (SDR) systems will range from low-cost terminals with limited waveform to multi-band, multi-mode, multi-channel systems that support advanced narrowband and wideband waveform capabilities with integrated computer networking features. The SDRs can tune to any frequency band and receive any modulation across a large frequency spectrum by programming the hardware. Currently, the JTRS has identified six waveforms to be supported in the radios, although more waveforms may be considered later.

SDR systems implementations tend to consume more power than hardware radios, and balance is the key to meeting the power budget. Multiple techniques to manage the power consumption and to achieve the needed balance can be used at the device level or applied at the system level.



STATIC AND DYNAMIC

It is important to distinguish between the two sources of power consumption: static and dynamic. The static power is present even when no logic operations are performed. The dynamic power is the power due to switching activities in the circuits. An aggressive power management strategy involves all system components: hardware modules, device drivers, operating system and application. Techniques to reduce both dynamic and static power in SoC designs are defined below.



The operating level of performance of a device can be categorized as zero performance, low performance, medium performance and high performance. Depending on the operating performance, the designers can use one or more power techniques to reduce power. (See chart).



SDR radios mostly operate in the medium or high performance levels when processing data or transmissions. As you can see in Figure 1, the adaptive voltage scaling (AVS) and dynamic voltage and frequency (DVFS) are recommended in the medium and high performance modes. AVS, the adjustment of voltage in response to performance needs, improves energy efficiency, but it compromises throughput.





Dynamic voltage/frequency scaling (DVFS) is the adjustment of voltage and frequency in response to performance needs of a core (DSP, ARM, DMA, etc.). When both clock frequency and supply voltage are dynamically changed in response to the load demands of the task, the energy consumed can be optimized for the low computational tasks while retaining the peak throughput for the high performance tasks.



The operating system (OS) can adjust the voltage and frequency in response to the knowledge of a system stage or predictions of the system workload. The ideal DVFS operates at the lowest voltage possible for each frequency. The voltage control must be under a power management device (hardware). The OS depends on the hardware to supply the voltage for the desired clock frequency. The voltage requirements vary with process variation and operating temperatures. DVFS is known to reduce dynamic power consumption by reducing the switching losses of the system due to the power dissipation in a capacitor.



POWER = ½ CV2F

The power in a dynamic system goes up by the square of the voltage and linearly with the switching frequency. According to the power equation, a reduction of the frequency by one-half provides a switching power reduction of a factor of two. At the same time, a voltage reduction of one-half will produce a switching power reduction of a factor of four.



The use of DVFS does not mean the lowest power consumption operating point. The use of DVFS causes increased leakage energy drain by lengthening the computational time. Therefore, for minimization of the total energy, the designers have to determine an operating point or critical speed for the specific task that provides the minimum energy consumption.



Designers must take the following into consideration:

• Account for static losses to find lowest operating power point.

• Look at how long the required software process will take to execute (number of clock cycles).

• There will be lower dynamic losses at lower clock frequencies, but the amount of time to perform the operation is longer and static losses will be incurred the entire time.



As you can see in Figure 2, the decrease in the frequency of operation with the voltage scaling results in an increase of the static energy consumption which can surpass the power savings provided by the DVFS. Special attention must be taken when using DVFS in relationship to the leakage power characteristics of the device.



CONCLUSIONS

There are several techniques used to minimize the total energy consumption in a battery operated SDR. DVFS is relevant when SDRs are operating in the different transmitting modes. System operating energy management can be maximized by DVFS to conserve battery life. While operating at a lower speed can increase the leakage energy contribution, system designers can use the critical speed to conserve energy in the system. It is clear that the OS of a SOC has a major impact on power consumption. The OS must implement the algorithms to take advantage of DVFS. Although this approach is going to take more planning and development efforts, the results will equip SDR providers with radios that would last longer in the field, and they would require fewer batteries and spare batteries.



About the author

Hector L. Rivera is system applications manager, HiRel defense and aerospace for Texas Instrument, Inc. Prior to joining TI, he worked at the Department of Commerce as an electronics engineer for the Strategic Trade Division of the Office of Strategic Trade and Foreign Policy Controls at the Bureau of Export Administration.

Click here for Illustrations:

Figure 1, Figure 2, Table 1