“In power the entire technology is now being driven from India”

ECN Asia recently spoke to Jyotirmoy Daw, Managing Director, Mentor Graphics (India) Pte Ltd at the Company’s Noida R&D center. Excerpts:

What is the range of Mentor Graphics R&D activities in India?

At our two Indian R&D facilities at Noida and Hyderabad, we are doing leading edge researches in many design areas. In functional verification, we are moving toward complete SoC verification. An area of verification becoming increasingly more difficult is emulation. Once SoC typically having 100 million gates is in place, the designer needs to find out whether all the hardware and software are functioning properly. At Noida we work on emulation compiler. Our transaction-based emulation accelerator that uses Mentor Graphics hardware and software can greatly increase acceleration. In low power design, we are working on simulation techniques. As the industry goes deeper into nanometrics, low power design has emerged as a very critical R&D activity. In a SoC, different segments of a device are put into sleep mode or part-operational mode depending upon their need, thus not only saving power but also reducing heat dissipation. We are driving some standards such as UPF (Unified Power Format) that enables designers define the problem, and EDA tools are developed to deal with the problem. Most of the low power R&D work is being done at Noida, as also work on advanced FPGA synthesis tool. At Hyderabad we do most of the work for PCB tools. DFT and co-verification of hardware and software are other important R&D areas. The work being done in India is at the leading edge. In power, for instance, the entire technology is now being driven from India. We hardly do any work on power in the US. What are India’s strengths and weaknesses as a global R&D center?

Designers can be said to fall into two categories: architects who conceive designs, and mainstream designers who take specifications from architects and convert them into final designs. India is good as mainstream designer but not as architect. Today most designs are conceived in the US and Europe and executed in India. India has a highly developed educational system, and in five to 10 years India should be capable of producing very competent architects.

How far is this criticism true that EDA companies for long failed to provide appropriate tools for deep nanometrics?

This seems just a matter of perception. There is a discontinuity between tools provided and tools adopted. EDA companies do bring out tools but their appropriate adoption takes some time. This situation is being remedied through partnerships between EDA companies, design companies, and foundries.

What is the level of investments Mentor Graphics has made in India, and what more investments are coming?

Now we are making an investment of $20 million per year, and this is expected to grow five to 10 percent per year.

The semicon industry is said to be slowing down in 2008. What are your projections for the EDA industry?

The EDA industry does not exactly follow the semicon wave but rather lags it. If in 2008 the semicon industry slows down, its impact will be seen on designs only in 2009 with reduced investments going into EDA tools in 2008. In 2007 the EDA industry is estimated at $5 billion, and is projected to rise by eight to 12 percent in 2008.

What are the main challenges Mentor Graphics envisages in the design world as designs go deeper into nanometrics and how is it addressing these challenges?

The rising level of abstraction makes verification a big challenge. Time to test a device is proportional to the number of vectors that you have to apply to a chip. The number of vectors increases by orders of magnitude at every processing node. Mentor has introduced a technology to compress the vectors. By providing compression levels exceeding 100X, Mentor’s new Xpress technology allows IC manufacturers to meet the quality objectives for advanced process nodes at 65nm and below without driving up the testing cost. Mentor has also been the first to announce a new technology in its Olympus-SoC place-and-route product that accelerates signal integrity closure and improves the reliability of manufactured silicon. MCMM (multi-mode multi-corner) signal integrity solution for 65nm and 45nm enables customers to address reliability issues such as crosstalk delay, glitch, power, and electromigration while reducing the time to achieve design closure. The Olympus-SoC product’s detailed routing and optimization engines have been enhanced to help eliminate SI violations concurrently over all variation scenarios. Challenges are many, and more are emerging. Mentor Graphics is geared to face them.