Stacked PoP: The future of packaging

Consumers expect electronic products to be compact in every aspect, and this has been the major driver for the move toward increasingly smaller consumer electronic products. As a result, companies are reducing the overall size of end-products, which is achieved by introducing smaller semiconductor packages. Therefore, the move toward smaller packages is becoming a major trend in the semiconductor packaging industry.

Stacked package is a promising solution offering high integration that leads to miniaturization. Among stacked packages, package-in-package (PiP) and package-on-package (PoP) are increasingly becoming important in the packaging industry, especially in mobile phone applications, as they enable the stacking of high-density logic devices. PoP solutions feature two packages with one placed above the other; solder balls are used to bond both these packages. This type of packaging results in the integration of logic and memory components in separate packages. For example, the integration of the application processor and the memory in mobile phones is achieved by using PoP solutions.PoP solutions contain two to four memory dies stacked on the top-package and one or two logic devices stacked on the bottom-package. The package height for the PoP solution depends on the number of dies encapsulated within that package. Presently, mobile handsets and digital cameras are stacking two packages for logic and memory architecture, while flash memory modules and high-density dynamic random access memory (DRAM) are stacking up to four packages more.

MAJOR ADVANTAGES

PoP solutions overcome the major drawbacks of die stacking, such as supply chain issues, yield losses, low die margins, and others. The demand for PoP solution is increasing in the industry because of their cost benefits, smallest package body size, mix-and-match logic with multiple memories, and flexibility of assembly. The following are the major advantages offered by PoP solutions:

• Increased functionality due to high wafer utilization helps to achieve more functionality in mobile devices

• Less substrate space occupation

• Faster time-to-market

• Short interconnects, leading to faster data transfer rates

• Smaller size and lighter weight, leading to board area reduction

• Design flexibility

• Fast signal propagation among chips

• Cost saving in every stage of the manufacturing process

TRENDS

The need for efficient memory architectures, such as high memory capacity and high performance in small area, and multiple bus issues demand high scalability. This demand and the requirement for high digital signal processing (DSP) capabilities are the major factors contributing to the significant expansion of PoP applications.

Outsourced semiconductor assembly and test (OSAT) companies such as STATS ChipPAC Ltd and Amkor Technology Inc. are the key participants in the PoP market, while a few original equipment manufacturers (OEMs) such as STMicroelectronics and Toshiba America Electronic Components Inc. (TAEC) have recently begun developing these packages as well. The pricing of PoP solutions depends on the memory configuration. A few of the latest PoP solutions introduced in the market are as discussed below.

In 2007 February, TAEC has introduced a new high-capacity memory solution that uses the PoP packaging technology. This solution has been designed to address the mobile handset segment. These solutions come in 14mm x 14mm and 15mm x 15 mm package dimension, and are compliant with the Joint Electron Device Engineering Council (JEDEC) standards.STATS ChipPAC Ltd has introduced its PoP solutions with top and bottom packages designed for handheld products, especially for mobile phones and PDAs. These solutions have a package height less than 1.6mm and are customized according to their applications. It is to be noted that STATS ChipPAC introduced its bottom PoP solution in 2005.

STMicroelectronics introduced its memory solutions using PoP technology in 2006. These solutions come in 12mm x 12mm and 14mm x 14mm package dimensions, and are designed to support both split bus and shared bus architectures. Spansion, a flash memory solution provider, introduced its PoP memory solution in the same year. These solutions come in 12mm x 12mm and 15mm x 15mm package dimensions, and have an approximate height of 1.4mm.

Increasing customer interest toward smaller and thinner handheld devices is expected to drive the market for PoP solutions. Furthermore, several new companies are expected to enter this market in the near future.

About the author

Jagadeesh Sampath is a research analyst in the semiconductors group of Frost & Sullivan. He focuses on monitoring and analyzing emerging trends, technologies, and market behavior in the global semiconductor industry. He has completed several research and consulting projects on power management ICs, VLSI design services, semiconductor packaging, and manufacturing. He also authors a number of articles on emerging technologies such as digital video broadcasting (DVB-H), digital power management, internet protocol television, and digital radio which are available at the www.semiconductors.frost.com Web portal. For comments or queries, please contact jsampath@frost.com.

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