Part one: ESD protection

Four long-term trends affecting the full breadth of the electronics industry have contributed to the growing importance of ESD protection within the overall practice of purposeful engineering for robustness. First, products provide many more points of entry for ESD strikes than they did years ago. This observation is particularly true of signal I/O ports but also holds for keypad, indicators, and displays—all of which are far more numerous as the sophistication and prevalence of user- and signal-I/O functions have grown.

Second, as IC fabrication processes have evolved from about 500 nm to 90 nm and smaller, integrated-device breakdown voltages have fallen dramatically. This corresponds directly with the reduction in operating voltages we’ve all witnessed, most dramatically in computational cores but also in I/O, memory, and analog circuitry. A casualty of this trend has been traditional protection devices, the threshold voltages of which exceed current-generation devices’ absolute maximum voltage-stress limits.Third, accompanying the reduction in integrated-device dimensions has been a dramatic increase in signaling frequencies. This trend has enormously improved the throughput of computational devices and the spectrum access of RF and photonic systems. As signaling frequencies increase, however, circuits are less tolerant of shunt capacitances. Unfortunately, by necessity all transient-voltage protection devices operate in shunt mode and thereby contribute a shunt stray in their non-operating modes.

Finally, the ongoing miniaturization of integrated devices has engendered an overall reduction in product dimensions as well. Shorter conductive traces provide lower stray inductances—a correspondence with both advantages and disadvantages. To the good, the smaller inductive strays result in lower coupling coefficients for current transients to adjacent circuits. The lower stray inductances, however, also increase the trace’s response to a current transient and lower the dynamic impedances of current paths.

FAILURE MECHANISMS

The best way to protect against a hazard starts with an understanding of its nature and the means by which it damages a system. Though it may seem counterintuitive, the fundamental nature of ESD damage is severe thermal overstress. The discharge event requires little energy to impart significant damage because it delivers that energy very quickly—far faster than the thermal time constant of common IC structures—and generally concentrates that energy in an extremely small volume.

Bipolar input devices, still used in high-precision and ultra-low-noise applications such as instrumentation front ends and analog signal processors, are particularly sensitive to voltage overstress. For example, a current-limited reverse breakdown of a base-emitter junction that leaves the device intact can nonetheless degrade the transistor’s gm (transconductance) and increase reverse leakage current. Less well-limited events can result in a base-emitter short, which renders the device nonfunctional.

MOS devices are significantly more susceptible to ESD damage than are bipolar devices and are ever more so with every reduction in a process’s minimum lateral dimension. As advances in process technology allow smaller and smaller lateral dimensions, gate oxide thicknesses also shrink. At 90 nm, oxides are only several molecular layers thick—an issue that has driven process developers to investigate alternative gate chemistries. Although the apparent dielectric strength of ultra-thin films is greater than that of thick films or bulk samples, the gate oxide’s breakdown voltage nonetheless falls as advanced processes implement thinner oxides. Should a transient greater than the oxide breakdown voltage appear on a MOS transistor’s gate with respect to the channel potential, the oxide will fail—an event called oxide punch through. Minor damage results in significant gate leakage. More typically, a short develops between the gate metallization and the channel, destroying the device.

Conductive films within an IC are also subject to ESD induced failure through fusing, resulting in open circuits. Fusing behaviors follow an I2t characteristic. With peak currents in as great as 30A, even a strike as brief as an ESD discharge can destroy titungsten or nichrome thin-film traces.

STANDARDS OF MEASURE

It is important to note that the most broadly accepted ESD immunity standards specify system level conformance testing. Test procedures do not generally apply to direct application of ESD strikes to IC pins. One exception is the old US MIL STD 883, which specifies a source model comprising a 100 pF charge store behind a 1500 ohm source resistance for testing at potentials as high as 2 kV. As has been the case with many ESD-immunity testing procedures since, the MIL STD 883 depends on an air discharge to simulate strikes emanating from a human body. Unfortunately, small variations in test execution and environment have long made test repeatability problematic for air discharge tests.

The ESD immunity norm most commonly in use today is the IEC 61000-4-2 standard. This system-level standard specifies a source model, comprising a 150 pF charge store behind a 330 ohm source resistance, and a specific discharge current waveform (Figure 1 and Table 1). The large charge store and low source resistance allow this source model to deliver more energy and greater currents than sources specified in older standards.

IEC 61000-4-2 provides for four test-severity levels. The first two levels are the least severe and are appropriate for permanently installed equipment that occupies a controlled environment with anti-static surfaces. This might include, for example, computer servers that occupy a controlled-access location with thermal and humidity controls. The third level is for equipment in uncontrolled environments that receives only occasional handling. An example of third-level equipment is a desktop computer that the operator only touches to power on at the start of the workday. The forth and most severe level is for equipment in uncontrolled environments that receives frequent handling such as your mobile telephone, MP3 player, or laptop computer.

The IEC 61000-4-2 test procedure accommodates both contact discharge and air discharge. Contact discharge provides more consistent and reproducible results. In cases where contact discharge is simply not practical, carefully document your test setup and procedure and test a sufficient number of units to assess variabilities in your test results.

Some IC manufacturers do make ESD immunity claims with references to standards and source models. Be careful to understand if these follow the MIL STD 883 procedure or a more modern standard. If the latter, also understand the circuit-board layout constraints to which these claims apply before accepting them at face value. An ESD immunity claim absent a reference test specification is meaningless.PRIMARY PROTECTION

Although IC pins are equipped with voltage-overstress clamps, those structures are too small and their locations are too far from the discharges’ points of entry for them to be effective as primary protection mechanisms. The system design, therefore, must include primary protection elements to shunt safely the energy from ESD strikes.

The protection device’s location is an important layout issue for ESD robustness. ESD immunity methods all depend on shunting the strike energy to ground—an event during which large currents flow, as Table 1 indicates. If you locate the primary protection device very close to the ESD strike’s point of entry—near an I/O port, for example—then the strike current flows through only a short length of PC board trace. If, on the other hand, you locate the primary protection device some distance away from the entry point, then the strike current flows through a longer trace length. In such an arrangement, the strike current can better inductively couple to adjacent traces including those that do not terminate on external ports, which would otherwise be safe from ESD induced stresses.

Similarly, your ground design must accommodate ESD strike currents as well the ground return currents that flow under normal operating conditions. This requirement generally suggests servicing protection devices with heavier ground traces than the design might otherwise warrant or using ground planes.

Carefully consider the specifications of your primary protection device. Component manufacturers characterize devices such as TVSs (transient voltage suppressors) with only a few parameters, but all must be appropriate for the particular line you are protecting. The rated working voltage or standoff voltage is the highest potential that the protected circuit should see during normal operating conditions. At voltages at or below the standoff voltage, the device’s leakage current should be at or below an extremely small specified value. The standoff voltage and its leakage current should apply across the device’s operating temperature range.

As the potential across the device increases above the standoff voltage, the shunt current will begin to increase. Device manufacturers specify a threshold called the breakdown voltage at a particular elevated shunt current. This threshold is typically 10 to 15 percent above the standoff voltage at room temperature and has a positive temperature coefficient of about 0.1 percent/degree C.

The TVS limits the protected node to the clamping voltage, which the device’s datasheet specifies at its peak impulse current—the device’s maximum safe operating current. The clamping voltage is typically 60 percent above the standoff voltage. Part of the voltage rise from the breakdown voltage to the clamping voltage is due to the temperature rise within the device as it dissipates the energy from the ESD strike. Conservatively sizing the device’s peak pulse power can minimize this contributor to the clamping voltage. Take caution, however, that the device’s shunt stray capacitance is proportional to its size.

A second contributor to the clamping voltage derives from the shunt current flowing through the device’s and the layout’s parasitic resistances between the protected node and ground. Keeping traces as short and as wide as practical reduces the IR term. Similarly, the very rapid current ramp at the strike’s leading edge working into the device’s and the layout’s parasitic inductances generate a dynamic contribution to the clamping voltage. Keeping traces as short and as wide as practical minimizes this dynamic term as well.

The next installment of Engineering on Purpose will examine minimum TVS sizing criteria and specific topologies for protecting various classes of signal lines.



About the author

Joshua Israelsohn is a co-founder of JAS Technical Media where he manages the company’s technical-communication consultancy practice. You may find his contact information at www.jas-technicalmedia.com/contact.

Click here for the illustrations:

Figure 1, Table 1