TI achieves 16-bit analog-to-digital converter and low-jitter clock combination

Texas Instruments Incorporated (TI) has introduced its 16-bit, single-channel, 135 mega samples per second (MSPS) analog-to-digital converter (ADC) and a low-jitter clock synthesizer. The combined signal chain solution provides system-level performance in communications, defense, and test and measurement applications. The data converter and clock are available on the same evaluation module (EVM) to facilitate fast evaluations of these complex systems. The ADS5483 ADC has the highest signal-to-noise ratio (SNR) and spurious free range (SFDR) over comparable ADCs on the market, for input frequencies from DC through the second Nyquist zone. Sampling at 135 MSPS, the ADC can achieve a SNR of 78.6 dBFS with 95 dBc SFDR for a 70-MHz input frequency (IF), which is up to 3.5 dB greater SNR or 8 dB greater SFDR over comparable ADCs.



In wide-bandwidth applications, the ADS5483 eases analog front-end design by incorporating a fully differential input buffer, a common feature across TI’s family of ADS54xx ADCs. Developed in TI’s BiCom3 high-speed process technology, this buffer provides constant input impedance over input frequency and eliminates kickback from the ADC’s track-and-hold structure to ensure consistent linearity of the signal. In addition, unlike competitive ADCs, the ADS5483 utilizes differential double data rate (DDR) LVDS outputs to significantly reduce the number of I/O traces and pins it consumes on FPGA or ASIC devices. The jitter CDCE72010 clock synthesizer provides additive jitter performance at less than 50 femtoseconds (fs), which meets the jitter requirements to clock high-speed ADCs, such as the ADS5483. For example, the combined EVM using the CDCE72010 and a crystal band pass filter to drive the ADS5483 at 122.8 MSPS achieves a high system-level SNR of 78.0 dBFS SNR and 89.1 dBc SFDR with a 100-MHz input frequency. The ADS5483 and the CDCE72010 are available on the same EVM to facilitate fast evaluations of complex systems. To provide designers with frequency planning flexibility, the EVM includes an open socket for the VCXO and crystal filter as well as bypass for an external source clock input.