Altera Launches DSP Builder Tool Version 8.0

Altera Corporation has announced its DSP Builder tool version 8.0, featuring second-generation model-based synthesis technology. This technology allows DSP designers for automatically generate timing-optimized RTL code based on high-level Simulink design descriptions. With this DSP Builder feature, designers can achieve high-performance design implementations, running at near-peak FPGA performance, in a matter of minutes.



Designing multi-channel signal processing datapaths in applications such as multi-carrier, multi-antenna RF processing in wireless basestations, the DSP Builder second-generation synthesis technology delivers dramatic productivity gains. The DSP Builder tool automatically adds pipelined stages and registers, and implements time division multiplexing to generate highly optimized designs for functions such as digital upconversion (DUC), downcoversion (DDC), crest factor reduction (CFR) and digital predistortion (DPD). This enhances productivity and enables users to perform system level design exploration rapidly, and to easily scale their design for varying carrier bandwidths, number of carriers, antennas, and sectors. DSP Builder version 8.0 includes design examples for multi-antenna, multi-carrier WiMAX and WCDMA DUC and DDC designs.



The DSP Builder is the synthesis technology for implementing Simulink designs in a high-performance FPGA platform quickly and effortlessly. Altera’s DSP Builder reads Simulink model files (.mdl) that are built using DSP Builder/MegaCore blocks and generates VHDL files and tool command language (Tcl) scripts for synthesis, hardware implementation and simulation. This technology shortens DSP design cycles by creating the hardware representation of a DSP design in an algorithm-friendly development environment.