Solutions for LCD TV super IP applications

Super inverters or high-voltage inverters for LCD TVs continue to draw tremendous amounts of market attention due to their high efficiency and lower cost. This article conducts a circuit analysis and reviews the practical design considerations for super IP converters in a 26-inch LCD TV application. It also explores transformer and circuit design in LCD TV applications.CONVENTIONAL BLOCK VS. SUPER IP BLOCK
In today’s LCD TV inverter designs, designers are usually seeking solutions that offer high efficiency, but at minimal cost. With conventional topologies, it is difficult to improve the efficiency without increasing the cost. As a result, super inverters or high-voltage inverters have been offered as a viable solution since these products save the main output’s rectification circuit. There are many different types of super IP topologies, but this paper focuses on one of the topologies shown in Figure 1, which is suitable for a 26-inch 4 U-shaped lamps LCD TV.

In the super IP block (Figure 1), the power stage and inverter stage have been combined into one stage to improve the total efficiency and save cost. The half- bridge block supply comes from the primary side of PFC 380V output, and T2 works as the primary side and secondary side separated transformer. The resonant tank circuit, which is made of series cap, T2, T3, T4, T5 and T6, as well as CCFL, converts the square-wave voltage to a sinusoidal output to drive the CCFL.

CURRENT BALANCE

U-shaped lamps are commonly adopted by panel suppliers to reduce cost and power loss, but both the U-shaped lamp terminals P1 and P2 request high voltage operation. However, it is difficult to detect the current sense as you cannot directly test the lamps series resistor voltage to discern the lamp’s current for both of the lamp terminals that are operating in high voltage. It is also difficult to control the 4 U-shaped lamps current balance with dispersed lamp resistor.

An inverter circuit consists of an inverter transformer, a lamp operating resistor, resonant caps, and a lamp parasitical cap clamp. Figure 2 shows the lamps’ current value with frequency variation.

It is interesting that the lamp current RMS value meets the f0 (resonant point), while the Rlamp is varied from 100K to 1MΩ, as shown in Figure 3. The f0 (resonant point) is decided by the L3, Clamp, C9 and C10. It means we can easily get current balance if the operating frequency is close to



Figure 3 shows a simplified inverter lamp circuit. The circuit consists of inverter transformer leakage inductance L, lamp parasitical cap parallel combined with outside caps C and lamp equivalent resistor R. The lamp current transfer function I(R) is expressed below.



If LC=1, then = is not related with R lamp value, we can make constant current inverter. The lamp current RMS value is decided by the Vs, the L inverter transformer leakage inductance, and the Clamp parasitical cap parallel with the outside cap value. We also learn the current curve around







is close if the



is small enough.



HALF-BRIDGE MOSFET SWITCHING FEATURE

Another issue is the half-bridge MOSFETs’ turn-on spike. Figure 4 shows the simulation waveform with a small duty cycle. There is big current spike when high side MOSFET (S1) and low side MOSFET (S2) are turned on. The turn-on loss of S1 and S2 is huge and the efficiency is not good. Switching noise is also a big challenge since it can negatively impact the overall system reliability.

First, assuming the half-bridge load is inductive and the current waveform lags behind with voltage waveform, D6 is the high side MOSFET S1 body diode and D7 is the low side MOSFET S2 body diode.

t0->t1: Before t
t1->t2: D6 starts to turn on, the transformer primary side current charges the 380V DC input power and the current is reduced to 0 at t2.

t2->t3: D6 turns off, the resonant between C15,TX6 primary side inductance, R65 and C45/C46 start, the switching node Vs voltage reduces to negative voltage make D7 turn on first, then the Vs voltage becomes positive.

t3->t4: The dead time finish, the high side gate drive turns on the MOSFET. There is a large current spike conducted at MOSFET Ids.

To reduce the current spike, we need to increase the V7 and V8 turns on duty to close to 50 percent to make the S1 and S2 ZVS. Then we can get square-wave voltage at the half bridge switching node.

The backlight PWM IC FAN7313 was selected as it provided all the control functions, such as soft start, open lamp regulation, open lamp protection, over voltage protection, short circuit protection, UVLO, and synchronization circuit with an external signal for a series parallel resonant converter. At the same time, external component count is minimized and system cost is reduced by integration. It also supports analog and burst dimming modes of operation.

The FAN7313 provides all the control functions for a series parallel resonant converter, as well as a pulse width modulation (PWM) controller to develop a supply voltage.

DESIGN PROCEDURE

1. Set first stage transformer T4 spec.

T4 separates the primary side ground and secondary side ground, and transfers 380V PFC high voltage to a middle square voltage +/-80V for secondary transformer input. T4 primary inductance should be large enough so that the C50 and T4 primary resonant frequency are smaller than the operating frequency 56K to let the inductance load for half bridge converter achieve ZVS.

First, choose C50 = 0.47uF/400V, set C50 and T4 primary inductance L resonant frequency to 7kHz, which is lower than the operating frequency 56khz. T4 primary inductance is



Choose T4 primary inductance = 1mH, and EER28L core with . The T4 primary minimum turns is



Choose Np = 60turns, T4 primary secondary turns is



Choose Ns = 26turns, so secondary output voltage is



2. Set second stage transformer T5 spec.

T5, T6, T7, T8 are the same transformers to convert the square voltage to square-wave voltage and then to a sinusoidal output to drive the CCFL.



First, we set the secondary resonant circuit frequency f0 = 65kHz, Q = 1, from (2.2. The leakage inductance is



Choose = 0.6H, and EEL17 core with . T5 primary minimum turns is



Transfer the T5 input square-waveform to sinusoidal wave. The sinusoidal wave RMS voltage is



From (2.3), the transformer turn ratio is



=23.29



We can then determine primary turns, turns ratio and the gap of core to get the required leakage inductance. For this application, the number of primary turns is 178Ts and that of the secondary turns is 4200Ts, whereas the turns ratio is 23.6.

3. Determine the required output capacitance C51, C77.

Assume a parasitic capacitance per U shape lamp is 5pF. Each parasitic capacitance is effectively in parallel with each of the output capacitors. The output capacitor C51 is



Choose C51 and C77 = 10pF.



With the consumer demand for highly efficient and cost-effective LCD TVs, high-voltage inverters need to provide efficiency at a minimal cost. This article explored an innovative solution that combines the power stage and inverter stage without a conventional DC-DC block after the PFC block. By using this advanced topology, LCD TV system efficiency and reliability were dramatically increased, while overall system cost was reduced.

References

• Jason Choi, Application Note “AN6017 LCD Backlight Inverter Drive IC（FAN7314)” Korea, Fairchild Semiconductor 2006.

• Datasheet FAN7313, Fairchild Semiconductor 2006.



Click here for the illustrations:




Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6