Drain current dynamic sharing of paralleled MOSFETs

The problem of dynamic current sharing among paralleled HEXFET MOSFETs has been addressed for many years. A deep insight of MOSFET turn-on and turn-off phenomena, as well as a good explanation of how paralleled MOSFETs behave as function of their characteristics and external layout, can be found in documents referenced 1 through 4.

However, these studies gave closed form analytical formulation only for static sharing, while semi-quantitative/graphical formulations were proposed for dynamic sharing. Moreover, these formulations included some approximations, were not easy to use, and did not allow for the impact of all parameter spreads. Correct utilization of modern computer-aided analysis allows the building of a more general and user-friendly simulation tool. A Matlab/Simulink model is presented here that allows simulating dynamical behavior of N parallel MOSFETs, runs on a standard PC and takes into account (some) parameter changes with junction temperature.

MODEL FEATURES

The model is of quite general use, even if its original development was aimed to analyze a low voltage automotive application inverter leg, where several MOSFETs in parallel were used to increase inverter current capability, as shown in Figure 1.

Load current is assumed to be constant (thus represented by a current source), which is usually the case when a high L/R load (like a motorfs phase) is driven by an M-phases inverter running at switching frequencies much higher than the L/R time constant. The starting point is the MOSFET model, completed with source and drain inductances. When considering modern inverters, the role of Ls may be as important as (if not more important) the role of Ld, especially when smd mounting technology is used. In fact, while source inductance is mainly dictated by the device itself and cannot be reduced below a certain value (usually 5-10nH per device), Ld may be, in principle, reduced gat willh by correct customer layout.

So, in the model, the effect of Ld is neglected. The set of equations used to model the MOSFET and the system is the following:

Equation 1:

id = Gf*(Vgs-Vt)^2 for Vds > ( Vgs-Vt)



Equation 1bis:

id = Gf * Vds * [2*(Vgs-Vt)-Vds] for Vds < (Vgs-Vt)











Equations 1 and 1bis describe the classical MOSFET model in the active region and ohmic region, respectively. Equation 2 takes into account the Miller effect. Because Ld is neglected, Vds dynamic is simulated, see equation 5, by assuming that the total load current minus the sum of all drain currents be used to charge/discharge high side and low side Coss (thus 2 x N x Coss), where N is the number of MOSFETs in parallel.

Equation 3 is self-explanatory, being the dynamic Kirchoff equation at the gate side of the MOSFET. Rg represents the external gate resistance, while Rgi represents the MOSFETfs internal one. For the sake of simplification, a lumped parameter approach is used. Finally, equation 4 takes into account the change of Vth with temperature.



The complete MOSFET model (except for equation 5) is shown in the upper part of Figure 2, while the model for the whole system is in the bottom part. The model does not represent the whole inverter leg, but only the glow sideh or ghigh sideh parallel of MOSFETs in Figure 1. This is justified because the dynamic sharing between paralleled MOSFETs will be checked, not the simulation of the whole inverter leg.

The behavior of the gotherh parallel of MOSFETs in the leg is considered later in this article.

The blocks at the upper left side of Figure 2 simulate gate driver designs when external R_C network decouples the gate driver from the MOSFETfs gates to reduce commutation speed and improve EMI. A number of MOSFETs are shown. All of them, except MOSFET1, are perfectly equal to each other, with parameters at one extreme of the manufacturing spread.

MOSFET1 has, instead, parameters at the other extreme. The left series of blocks represent equation 5. The load current is dynamically modulated as a function of Vds during turn-on transient, to keep into account body diode recovery of the parallel of MOSFET, in the same leg, which is being turned-off. The bottom area of the scheme takes care of dynamic power dissipation and gpower dissipation sharingh calculation. The model is not able, for the moment, to account for dynamic change of intrinsic MOSFETs capacitances with drain to source and drain to gate voltages.

A PRACTICAL EXAMPLE

The model is used to simulate dynamic sharing for seven IRF2807Z in parallel to each other, in a three-phase brushless motor drive inverter. Total current (Iload) is 300A, and Vdc = 48 to 56V. Simulated Vgs waveforms agrees quite well with measured ones, except for the duration of the gplateauh region, which is slightly shorter in the simulation, due to the present modelfs limitations in accurately representing Cxss dynamic changes. Three lots are considered, whose Vth and RDS(on) (hence Gf in the ohmic region) distribution has been measured at final test. Production spread of intrinsic capacitances is expected to be negligible in IR trench MOSFETs, due to the excellent manufacturing process control of gate oxide thickness. On the other side, spreads in Vth and gfs cannot be neglected.

The following values for Cxss are considered:

Ciss = 3270pF

Coss = 440pF (equivalent capacitance in the 0-60V Vds range)

Crss = 230pF

Vth temperature coefficient is derived by data sheet and is around -9 mV/‹C.

Worst case spread in Vth and gfs over three lots is shown in Figure 3. These are values at 25‹C. In the model, Vth(Tji) and gfs(Tji) have to be considered, where Tji is the average steady state junction temperature.

Another question is if both Vth and gfs worst case spreads have to be considered simultaneously or not. By close examination of the three lots data, it was found that no special correlation between these two parameters do exists. Hence, worst case analysis shall consider Vthmin/gfsmax and Vthmax/gfsmin combinations.

Figure 4 show simulation results when worst case conditions are applied.

In Figure 4, gpowunbh represents the dynamic power dissipation unbalance, for a given switching frequency. This parameter is obtained by integrating Vds(t) and Id(t) and then multiplying the result by Fsw. So, its value at the end of the simulation period has to be read.

In this example, M1 will, in average, dissipate 112W more than the other MOSFETs. By considering its Rthjc ( 0.9‹C/W ) this means roughly 100‹C difference. Such difference, by itself, could get M1 well beyond Tjmax. Moreover, Tj increase will, in turn, decrease Vth1 of about 0.9V, further worsening the unbalance situation. This effect is, partially, compensated by a decrease of gfs with Tj:

a) RDS(on) increases with Tj. This actually decreases the equivalent Gf in the ohmic region.

b) Gf in the linear range also decreases with Tj increase, as shown in the data sheet.

Because the model does not allow timeliness simulation of more than a few switching cycle, occurrence of thermal runaway problems cannot be highlighted. Fortunately, there is another quicker way to check for runaway occurrence.

Any ∆Ploss generates a ∆Tj which, in turn, generates a -∆Vth and a -∆gfs. In turn, -∆Vth generates a positive ∆P variation, while -∆gfs generates a negative ∆P. There is thus a feedback loop whose overall phase shift can be positive or negative, depending on which between the two parameters variations (Vth or gfs) dominates.

The overall loop gain is given by:



Gloop = (kVth*Ý∆Ploss/Ý∆Vth +kgm*Ý∆Ploss/Ý∆gfs ) * Rthjc.

Partial derivatives may be obtained by running simulations multiple times, each time changing the value of one parameter to a new value determined by the temperature change calculated by the previous simulation.

Apart from predicting design criticalities with respect to a devicefs parameters spreads, the model can be successfully used to point out other criticalities, like excessive source parasitic inductances due to layout, or non-optimized design of the gate driver stage.

It is well known, in fact, that, increasing turn-on and turn-off speed, dynamic sharing can be improved. The model quickly allows checking for the effect of switching speeds upon dynamic current sharing.

CONCLUSIONS

A model for simulating drain source current dynamic sharing for MOSFETs in parallel has been presented. Despite its simplicity, and the level of approximation introduced, such a model can be used to quickly identify potentially critical situations when several MOSFETs are placed in parallel to each other, especially in inverter applications. This model has been successfully utilized to solve a number of critical applications where severe MOSFETs damage occurred due to non optimized design.

References

1. International Rectifier AN941: Paralleling HEXFET Power MOSFETs

2. International Rectifier AN947: Understanding HEXFET Switching Performance

3. International Rectifier AN1001: A More Realistic Characterization of Power MOSFET Output Capacitance Coss

4. J.B.Forsythe: gParalleling of Power MOSFETsh; IEEE-IAS Conference Record, October 1981.



Click here for the illustrations:




Figure 1, Figure 2, Figure 3, Figure 4