Design tips cut FPGA power use

Tips and tools from FPGA vendors help engineers reduce power in complex designs.

Overall, the latest generations of FPGAs provide the performance engineers need for new designs. And FPGA vendors complement performance with power-saving techniques. In many cases, FPGA design tools consistently aim to implement low-power circuits, but engineers can select performance vs. power tradeoffs as well. Most of those low-power changes occur within the design tools and do not cause engineers to rework their code. But before anyone tries to reduce power, they must understand where the power gets burned. It makes no sense to reduce power consumption in an area that doesn’t burn that much power to begin with. Power divides into two classes – dynamic power and static power. The power equation P= ½CV2f shows that the smaller capacitances and lower voltages of smaller-geometry FPGAs decrease dynamic power consumption even as clock frequencies increase. Still, engineers can use design tools to reduce dynamic power consumption. FPGA manufacturers have worked hard to also reduce static power consumption – the power that arises from simply powering a circuit. According to several FPGA manufacturers, static more than dynamic power has become the power you must give the most attention.

To help engineers better understand power consumption, FPGA manufacturers supply two tools, an early power-estimation tool and a post-place-and-route power-estimation tool. Typically, an early-estimation tool asks engineers to enter information, such as numbers of gates, memories, multipliers and other elements as well as types and numbers of I/O connections. They also enter information about clock frequencies, toggle rates and so on. The tool then estimates power use based on the manufacturer's characteristics for the chosen FPGA. At this stage, engineers can approach I/O ports, memory configurations, and logic in different ways to determine how changing a design will affect power use

After going through place-and-route steps, engineers can get a more accurate power-use report based on their implemented design. The design now includes specific clock-tree paths, device locations, signal routes, and I/O devices. A post-place-and-route power tool also can report power dissipation associated with specific clock trees, I/O devices, power rails, and logic blocks. So, engineers can look at the places where their FPGA uses the most power.

Based on their power analyses, engineers can use their design tools to make tradeoffs that reduce power and still keep performance within design specifications. As noted earlier, engineers can have FPGA design tools automatically adjust a circuit to minimize power.

The following design tips will help you save power in an FPGA design. But because FPGAs offer different capabilities, architectures and features, some of the tips below may apply to specific devices. Even in those cases, this information may prompt other power-saving ideas. These tips came from conversations with experts at FPGA manufacturers. (Please see our acknowledgments.)

• Pay attention to I/O pins. If signals will not change state often, use a pull-up or pull-down circuit that uses the least power but still maintains a pin in its proper state. Lattice, for example, provides a bus-keeper function for this purpose. Power savings may seem small until you multiply them across a 64- or 128-bit bus. When a design has unused I/O banks, if possible, don't connect their power or turn their power off.

• Reduce drive voltages. If you can use a 1.2V LVCMOS interface instead of a 3.3V LVCMOS interface you save considerable power because voltage gets squared in the power equation.

• In some cases, specs will dictate a bus type, but when possible, replace wide FPGA-to-FPGA buses with serialize-deserialize (SerDes) connections. Some FPGAs now provide low-power multi-gigabit/sec SerDes interfaces.

• Reduce the number of clock trees, or clock spines, in a design. Turn off or disable unused clock lines or branches. This technique reduces the clock's capacitive load and can save considerable power in a clock driver.

• Look at peak power. A cycle-by cycle analysis can help you focus on states that use a lot of power. Suppose your design will include a 4-Kbyte memory. You implement eight separate 1-bit-wide memories, each 4 Kbits deep. To read or write a byte, your circuit must simultaneously access all eight memory banks. As a power-saving alternative, create eight 8-bit by 512-byte memories with common address lines and a separate enable signal. Thus you can enable one byte-wide memory block at a time rather than all eight 1-bit-wide blocks. (FPGA tools often provide this type of trade-off as a design option.)

• Move to DDR3 SDRAM. If your design demands large amounts of external memory, consider DDR3 SDRAM devices in DIMM packages. Designing your own DDR3 interface can get tricky, though, so look for FPGAs that can easily include a ready-to-go DDR3 interface for DIMM packages. The DDR3 memories operate at 1.2V vs. 1.8V used for older DDR2 memories. So you get an immediate power saving. Dynamic signal termination also helps reduce power consumption in an FPGA that connects with DDR3 SDRAM modules.

• Use Gray codes to implement state machines. This coding technique changes only one bit per state, for example, 000, 001, 011, 010, 110, and so on. Thus, state changes never go through a transition such as 011111 to 100000, which switches all bits lines simultaneously and uses more power than a single-bit transition.

• Configure I/O ports on the fly. If your application does not use an I/O interface very often, reprogram it to a low-power mode during its idle time. A number of blocks in FPGAs from Xilinx, for example, can switch from LVDS or HSTL (high-speed transceiver logic) mode to temporarily act as LVCMOS (low-voltage CMOS) blocks.

• Move external functions into an FPGA. Don't leave ancillary logic ICs on a board if you can implement their operations in an FPGA. Some FPGAs require external flash memory or EPROM for programming. That memory uses power, too. Eliminate as many external support ICs as you can from a design.

• Take advantage of standby or suspend states. FPGAs may provide an external connection or a programmable mode that puts the device in a low-power standby mode or even in a no-power mode. The Mach XO family from Lattice, for example, offers a control pin that drops a device into a low-power mode. Recovery takes about 100μs. Actel's ProASIC and Igloo FPGAs provide a similar input that puts a device into a Freeze Frame mode that gates off clocks and inputs and places outputs in a high-impedance state. Internal registers, logic and memories maintain their states and information. The Xilinx Spartan FPGA family operates in two power-management modes; suspend and hibernate. The suspend mode maintains internal FPGA settings, so a circuit can quickly go into and out of a low-power suspend mode. Hibernate, on the other hand, reduces power effectively during relatively long periods of inactivity. In the hibernate mode, a Spartan FPGA requires no power.

• Account for inrush current. SRAM-based FPGAs can draw large currents as they go through a power-up sequence and configuration steps. Currents range from 10's to 100's of milliamps over 100's of microseconds. If inrush currents present a problem choose a nonvolatile FPGA or add external components that limit that current and extend battery life in portable devices.

• Batteries care about power not current. Suppose that in standby mode FPGA X draws 3μA and FPGA Z draws 30μA. That amounts to a 1-to-10 current ratio. But device X operates at 1.2V and Z operates at 1.8V. The power dissipation comes to 3.6μW vs. 54μW, for a 1-to-15 power dissipation ratio. Pay attention to current times voltage.

AcknowledgmentsB>

For contributing design tips and more information than we could publish, our thanks go to Fares Mubarek, Actel's senior VP of engineering and marketing; Paul Ekas, senior manager of product development for Stratix FPGAs at Altera; Gordon Hands, director of strategic marketing and Mike Hendrick, software product planning manager at Lattice Semiconductor; and from Xilinx, Matt Klein, principal engineer, Mark Moran, senior strategic marketing manager and Hitesh Patel, director, software product marketing.

For more information

• "Power Saving Design Techniques with Low Cost FPGAs," Lattice Semiconductor Webcast. www.latticesemi.com/corporate/webcasts/powersavingdesigntechniqu/index.cfm

• "Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces," Altera. www.altera.com/literature/wp/wp-01034-Utilizing-Leveling-Techniques-in-DDR3-SDRAM.pdf





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