Panasonic and Renesas Technology to Collaborate on Development of SoCs at 32-nm Process Node

Panasonic Corporation and Renesas Technology Corp. are now collaborating on the development of elemental process technologies for SoCs of the 32-nm node. The two companies are confident that their 32-nm node transistor technology and other advances can soon be applied to products in mass production. The 32-nm SoC process employs a developed transistor technology with a metal/high-k1 gate stack structure and interconnect technology, using a low-k2 material. To achieve a device using complementary metal-insulator semiconductor (CMIS)3 technology, a type of complementary Metal Oxide Semiconductor (CMOS), at a 32-nm node, an ultrathin film cap layer4 is applied at the atomic level to transistors with a metal/high-k gate stack structure under optimized conditions. This allows development of a conventional transistor configuration, employing an oxidized silicon film as the gate insulation layer. The introduction of the cap layer has been shown to improve transistor reliability in practical use and suppress distribution of electrical characteristics between transistors, thereby enabling the operation of large-scale circuits.



The two partners have been working on the joint development of SoC technology, even before the establishment of Renesas Technology. Their joint development work has yielded impressive results until now. They developed a 130-nm DRAM composite process in 2001, a 90-nm SoC process in 2002, a 90-nm DRAM composite process in 2004, a 65-nm SoC process in 2005, and a 45-nm SoC process in 2007. The l development on the 32-nm fabrication process will be applied to SoCs for advanced mobile and digital home appliance products. Building on their accumulated technology expertise and resulted advances, as well as their successful partnership of many years, Panasonic and Renesas Technology hope to continue efficiently developing the advanced process technology that can be quickly moved to mass production respectively.