Extremely high speed analog-to-digital converters (ADCs) are critical components that make broadband digital receivers for communications, radar, electronic warfare, radio-astronomy, and high bandwidth oscilloscopes possible. The common element in each is the clock source and clock distribution circuitry, despite significant differences in the front-end architecture. In an ideal world, the clock that samples the analog input is perfectly periodic. Unfortunately, noise-induced variations in the clock signal create ambiguity in the sampling intervals, which results in uncertainty of the sampled signal amplitude.
This article focuses on very low jitter clock distribution circuits for broadband ADCs and will examine:
• Resolution limits imposed by jitter of the clock source and the clock distribution circuitry;
• Measurement of the clock distribution circuits’ noise and how phase noise is converted to residual jitter; and
• Measured results of the Inphi 13616CF 1-to-2 clock fan-out circuit, which demonstrates a very low 25fs RMS random jitter.DERIVATION OF JITTER INDUCED RESOLUTIONS LIMITS
Consider the receiver front-end architecture depicted in Figure 1 in which a broadband track-and-hold (T&H) amplifier samples a several GHz carrier and drives a several Giga sample per second (GS/s), 8-bit ADC. Commercially available, fast 8-bit ADCs typically have 3dB analog bandwidths of about a couple GHz. In a receiver designed to digitize signals greater than a couple GHz, one must first down-convert the signal to frequencies within the analog bandwidth of the ADC. Traditionally, this is achieved by using a mixer and a local oscillator. More recently, broadband T&H amplifiers (Figure 2) have been introduced with analog bandwidths as high as 18GHz. These T&Hs exploit very high frequency bipolar technologies and obviate the need for mixers in some receivers. In order for a receiver to take advantage of this performance, however, the T&H must be strobed with a clean clock.
Referred to as sample jitter, aperture jitter or aperture uncertainty, the effect of uncertainty in the sample time on a data converter’s resolution can be understood by considering the signal in Figure 3. Uncertainty, Δt, in the time that the signal is sampled, results in an amplitude uncertainty ΔV. Intuitively, it is easy to see that the lower the slew rate of the input signal, the greater the sampling error. Note that it is the frequency of the sampled signal, not the frequency of the sampling clock, which determines the amplitude uncertainty.
An equation that relates the amplitude uncertainty or resolution limit to the frequency of the sampled signal is derived by first defining the acceptable amplitude error to be ˝ of a least significant bit (LSB). So, for an N-bit ADC whose full-scale range (maximum allowed input amplitude) is Vfs, the acceptable RMS amplitude error, ΔV, is
When attempting to digitize a signal whose frequency is f and whose peak-to-peak amplitude is equal to the full scale range of the ADC, Vfs. The signal amplitude as a function of time is given by
and the maximum slew rate of the input signal, obtained by differentiating Equation 2 and evaluating the result at its maximum, is
Substituting Equation 1 into Equation 3 and solving for Δt yields,
Notice that this expression is independent of the full scale input amplitude of the converter. Solving this equation for N (the number of bits of resolution) yields:
To summarize, Equation 5 provides the theoretical limit of the resolution of an ADC that is digitizing an input signal of frequency “f” with a clock whose RMS jitter is Δt. Figure 4 depicts this result for three values of RMS jitter. The maximum input frequency of interest is plotted on the abscissa. It is seen that clock jitter of 100fs limits the resolution of a 10GHz input to 7 bits and a 1GHz input to about 10 bits. Although highly tuned oscillators with several hundred fs of RMS jitter exist and could be used as the clock source for a 10-bit, 1GS/s ADC, maintaining clock stability through on-chip clock buffers to the track and hold and comparators is problematic at the 10-bit level.
CIRCUIT NOISE AND NOISE MEASUREMENTS
Given a very clean clock source, the job is to distribute the clock without adding significant jitter. There are numerous sources of jitter, and they fall into two categories: random and deterministic. This article is concerned with clock signals of between several hundred MHz and several GHz and assumes that deterministic jitter has been effectively eliminated.
In receivers in which multiple ADCs are used, phased arrays for example, the clock distribution network may consist of several stages of fan-out buffers. Each stage adds random jitter to the clock. The random jitter from several serial stages sums in an RMS fashion, so it is critical to keep the added jitter of each stage as low as possible. Random jitter is caused by fluctuations in charge carrier (electron) concentrations, and these fluctuations follow Gaussian statistics. As such, the various sources of random jitter within a circuit also sum in an RMS fashion.
Different noise generating physical phenomena have differing frequency dependencies. Thermal noise generated in resistors, both the access resistances of transistors and resistors used in the circuits (e.g. bias, termination, and load resistors), is frequency independent or “white.” Shot noise is the noise generated in semiconductor junctions and is also white. Flicker noise is inversely related to frequency. The net effect of these noise phenomena in a clock buffer is phase modulation (PM) of the clock signal, and the added (PM) noise is termed the residual PM noise. Phase noise is a frequency domain measurement. The added random jitter (a time domain parameter) of a circuit is related to the integral of the residual PM noise.
Figure 5 shows the block diagram of the test setup used for measuring the residual PM noise of a pair of clock fan-out circuits. The 13616CF is a broadband (DC to 13GHz), differential, 1-to-2 fan-out circuit with current-mode logic (CML) inputs and outputs. It operates from a -3.3V supply and ground. It is suitable for distributing clocks and data at input amplitudes from 300mVpp to 2Vpp differential. Though not specifically designed for applications in which very low added random jitter is key, it turns out that the 13616CF and its positive supply version, the 13617CF, are good candidates for the job as we will see.
The input signal of 10GHz was taken from a very low noise sapphire loaded cavity oscillator, amplified and leveled by a low PM/AM noise array amplifier. The amplified signal was then split using a hybrid into in-phase (00) and out-of-phase (1800) components which were finally used to drive the two 13616CF fan-outs differentially. The measurements were made with differential inputs to each fan-out. The output of each fan-out was taken single-endedly from one of the two differential output stages. Measurements were made at 5GHz and
10GHz and with input powers of -9dBm and +4dBm. The output of each fan-out was then amplified and fed to a dual-channel cross-correlation PM noise measurement system as shown in Figure 6.
Each channel of the measurement system is comprised of a power splitter, a phase shifter, and a phase detector (PD). The phase shifters establish true phase quadrature between two signals at the PD inputs. The output of each PD after amplification was fed to a dual-channel cross-correlation fast fourier transform (FFT) spectrum analyzer. The advantage of this technique is that only the coherent noise – that is, the noise of the device under test (DUT) – present in both channels averages to a non-zero value. The time average of the incoherent noise processes approaches zero as N, where N is the number of averages used in FFT. A precision AM/PM modulator is used to calibrate the phase sensitivity of the measurement system.
The measured residual phase noise of the Inphi 13616CF clock fan-out circuit is shown in Figure 7. Significantly, the white noise floor is -159dBc. Also shown is the noise floor of the system – that is, the noise measured without the fan-outs in the test system. The plots show 60Hz and its harmonics as well as few spurs at higher offset frequencies (foffset >10kHz). These spurs are contributions from the measurement system and are not from the fan-outs as demonstrated by their presence in the noise floor spectrum.
Further, Figure 6 shows that there is an increase in PM noise between offset frequencies 2MHz and 9MHz. This is due to an unavoidable delay mismatch between two inputs to the phase detector in each channel of the measurement system. It is not a PM noise contribution of the fan-outs as demonstrated by its presence in the noise floor measurement. The white PM noise level is estimated by the lowest level, in this case, the region around 1MHz.
The residual random jitter, τj, is calculated from the phase noise by integrating the single side-band phase noise, L(f), according to Equation 6. The limits of the integration are from 1Hz offset to the 3dB small signal bandwidth of the fan-out which is 8GHz.
Applying Equation 6 to the phase noise spectrum of Figure 6 yields 25fs – a very low result that, referring to Figure 3, would enable data converters to digitize 10GHz signals with 9-bit resolution.
CASCADING FAN-OUT STAGES
For sinusoidal clocks of lower frequency, the added random jitter of the 13616CF increases because the slew rate of the input decreases. This can be understood by referring to Figure 2 again. Noise processes, which cause fluctuations in the signal amplitude (ΔV) result in fluctuations of the signal’s phase or, equivalently, zero crossing (Δt). If the slope of the input signal is less, as it is for lower frequency inputs, then the same fluctuations in amplitude will cause greater fluctuations in phase.
Now, if the 13616CF were a low gain, linear buffer, and the clock amplitude was such that the signal chain through several buffers did not saturate, then the jitter through several cascaded 13616CFs would be the RMS sum of the jitter in each stage. For N stages, the total added jitter would be the square root of N times the jitter in one stage.
However, since the 13616CF has high gain, good limiting characteristics and has very fast output rise and fall times (15ps typical), the total jitter added by a cascaded chain is significantly less than the square root of N times the RMS jitter of the first stage. Instead, since the output slew rates of the first and subsequent stages will be commensurate with a 10GHz to 15GHz sinusoid, the added RMS jitter of the first stage will be significantly more than that of subsequent stages. For example, the 13616CF will add approximately 50fs of random jitter to a 5GHz sinusoidal clock source of 1Vpp. If three stages of the 13616CF were used in a clock distribution network for driving eight ADCs (in a portion of a phased array receiver, for example), the contribution of the second and third stages would be a little less than 25fs each. Thus, the total added jitter of this three-stage clock distribution network would be the square root of (50^2 + 25^2 +25^2) = 61fs.
Because it adds very little random jitter to its input, the 13616CF is ideal for distributing clock signals to very high bandwidth, high sample rate ADCs.
Acknowledgements:
Thanks to Archita Hati and David A. Howe of NIST’s Time and Frequency Metrology Group for their assistance in making the phase noise measurements.
Click here for the illustrations:
Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7 |
