Paralleled MOSFET: General suggestions for a good match

The objective of this article is to deal with paralleled power MOSFETs in switching and analog applications. The topic will focus on the reasons why electronic suppliers should use paralleled devices, and based on theory and on electric test bench, it will show the possible advantages and disadvantages during actual work conditions. In addition, it will highlight the principal parameters to optimize the work itself.In all types of power applications that use power MOSFET devices in switching operations, when the management of total current is too high for a single switch and it is impossible to use a single power MOSFET (because the size of the device itself could become very high and economically not satisfying), it’s common practice to use two or more devices in parallel in which the total current is shared amongst them.

When power MOSFETs are soldered in parallel and close to being thermally coupled, the current that flows in each single device depends, in first analysis, on the R_dson of the device itself and the voltage drop between the drain and the source. The parallel condition imposes that all devices in parallel should have, time by time, the same drop voltage based on the picture showing the same V_dson (Fig. 1).

The condition:

V_ds1 =V_ds2=•••••••••••• V_dsi (1.1)

Where the Vdsi is the single voltage drop between drain and source pins, the voltage drop of resistances and parasitic inductances due to wire and tracks are neglected. If we consider them, as shown in Fig. 2, the parallel condition becomes more complicated because the resistances and parasitic inductances don’t have the same values since they depend on a schematic layout.

The matching points of all currents are important because on the matching points, the voltage drops are the same. However, they include the sum of all impedances (during a normal switching) that currents face during flowing.

In general, if the R_dson of each device is bigger than the parasitic resistors, the current’s distribution is not affected by the parallel devices themselves. Instead, if the R_dson is comparable with parasitic resistors, then accurate pin position during the layout definition is what provides proper current sharing.

An example is the following picture, taken by a FLIR thermal camera, on a board that uses four power MOSFETs, in particular the PolarPAK (a registered trademark of Vishay/Siliconix) STK822 device with R_dson max is 2.15m at V_gs = 10V. As shown, the total current is poorly distributed between the four devices. This is caused by the position of the pins on the board. In fact, because of high resistive path in the current flowing, the first device on the left, glowing red, is forced to manage most of the current, which results with a higher temperature increase than the others.

In this case, the parallel is inadequate because the first device will have to bear the brunt of an increase in the total current, perhaps cascading down the line to the other devices. In fact, in this case, the test on the board was done with low current and a low temperature fixed at 55ºC.

A good compromise is shown in Fig. 4. In this case, the current flowing through each device has approximately the same resistance path, and if the devices’ Rdson are about the same, the current distribution will be well balanced.

BENCH MEASUREMENT

If the electrical board layout is optimized, the parallel MOSFET operation is affected by other parameters, as shown in Fig. 5.

The diagram shows an electric bench test made on three STB210NF02 devices, put in parallel, which load is a 10H inductor. The three devices are driven by a single driver, with the on/off driving resistor realized by three trimmers to best fit the switching conditions for the paralleled devices.

In Fig. 5, the three upper devices, all with the same part number as the ones below them, are used as free wheeling diodes for the inductor L during the switching off period. Before performing the test, the devices were measured by a curve tracer and focused on the following electrical parameters:

• Threshold voltage values Vgs

• Output characteristic at low Vgs values

After that, more tests were performed to create balanced and imbalanced conditions modifying the driving output parameters.

The first devices tested (Fig. 6) were chosen with different threshold voltages in order to clearly indicate the different working conditions.

In Fig. 7, the Vgs and I_ds current waveforms of the three devices are shown. The three currents are slightly imbalanced because of different threshold voltage. In this case, the first device is flown by a higher current at same V_gs than the second and third.

When devices are used in parallel, the perfect balance of currents is challenging, but it is possible to choose the proper driver output resistors for turning on and turning off to try to obtain some benefits in terms of current sharing. The driver resistors were set to 0 for this test.

In Fig. 8, the waveform indicates that the increased value of driver resistors, especially the turn off one, could intensify the imbalance of the three currents.

This situation was obtained by choosing the 100 turn off driver resistor and 0 the turn on one. In general, the device with the highest current gain and lowest V_th (if used in parallel) is the first device to turn on and the last one to turn off. But, in this case, the turn off is more stressful, and as shown, the imbalance is more evident.

This phenomenon is caused by the fact that during turn off. The second and third devices reduce their currents, and at same time, they flow by the first device because the current is forced by inductive load.

In Fig. 9, the driver resistor turn off of the first device is put at 15, which is the minimum value to observe the first current peak. To summarize, the current imbalance is affected by the following parameters:

• Driver resistors for turn on and turn off

• Length of wires

• Parasitic inductance

• Distance of resistors from the gate pad

Moreover, it is important to highlight that although devices have the same part number, they generally have some small differences that, when used in parallel, can cause current imbalance phenomena. This means that even if the same devices are selected for paralleling, it will be almost impossible to have a perfect match, so a parallel connection can be attained with the minimum imbalanced current, as dynamic or as static. A gate resistor could help for this objective because it separates the working operation into two parts – turn on and turn off – and is important that those resistors are located next to gate pins.

Different devices, based on their behavior, are defined by the I_ds-V_gs curve at various junction temperatures (see Fig. 10). When the V(gs) is less than V(gs) at zero-tempco and at a fixed value, if the temperature increases, the current also increases. The opposite occurs when V(gs) is greater than V(gs) at zero-tempco. The “zero tempco” is the temperature matching point of curves V_gs-I_ds at a fixed V_ds value. If the device is working exactly at “zero tempco” point, the current I_ds remains constant at temperature change.

These curves are important because during switch on and off, the device V_gs can be higher or lower than V_gs “zero-tempco”. It can happen at V_gs < V_gs “zero tempco” that the junction temperature increases by a continuous current increase. This is more probable when devices are placed in parallel, especially with high V_ds, because when there is an imbalanced current and the V_gs is below the “zero-tempco”, the power dissipation increases and could bring the device to thermal runway (as shown in _{Fig. 10}).

Another phenomenon is the oscillation that can occur between gate-source during switching operation. In general, this happens when the device has low R_dson, low V_dss, high V_gs, high G_fs and parasitic inductances of the tracks. The oscillations generally involve all power MOSFET pins and could be very dangerous – especially between gate and source because the voltage spikes can exceed the maximum V_gs rating. If the devices are placed in parallel, the electric tank of all parasitic inductances could amplify the oscillations. In general this behavior is reduced by the proper choice of gate resistors, which could help in smoothing out the oscillations that are due to the resonant RLC stray path.

We complete our analysis, addressing the parallel in linear mode operation. In a power MOSFET, the linear zone is defined by the working condition V_ds≥V_gs-V_th where V_gs is the gate-source voltage applied to the device and Vth is the threshold voltage. In general, this working condition could be very dangerous for MOSFETs, for at least two reasons: thermal runaway and hot spot phenomena.

Thermal runaway is a quick rise in temperature of the device junction, caused by power dissipation, and generally it’s linked to the on resistance and threshold voltage. The on resistance increases with the junction temperature resulting in power dissipation. Moreover, the increase in temperature causes a reduction in V(th) and then an increase in current. The junction temperature increases until the device achieves the thermal equilibrium in the system by the heat-sink, the fan, or some other method.

If the heat removal system is inadequate, the junction temperature increases more and more until the device fails. This working condition is very unstable for devices and happens when the V_gs device is lower than the “zero tempco” point. In this case, when the temperature increases, the current increases because the V_th also decreases, so there is a positive feedback that could lead to the device failure. This phenomenon could be more evident if the devices are put in parallel because the sudden temperature increase and consequently the increase in on resistance could produce the device failure without the other devices could balance the total current sharing. This kind of failure produces the so-called ‘hot spot’ – a small area of the silicon is burned where locally this kind of positive feedback is focalized.

Now that this has been explained, we show the results of an electrical test made on the STV270N4F3, in which devices work in linear mode. The test was performed with two devices in parallel, as shown in Fig. 11.

The test was performed on 50 samples – each chosen and tested by automatic test equipment (TESEC tester). The screening performed on the samples was the V_p test, in which conditions were V_ds = 2V at several I_ds currents. The V_p test is the measure of the V_gs when the V_ds voltage and I_ds current are fixed. The devices during the testing were marked with a serial number, starting from “1” to “50” and after that, ordered by V_gs at I_ds = 20A, and by G_fs. The device parameters are summarized on the following pictures.

The bench test was submitting the DUT (two paralleled STV270N4F3) to an electrical power pulse to monitor the current sharing during the switching. The test was done to attempt to achieve the following electrical conditions:

• V_ds = 2V

• I_ds = 20-30A

• T_pulse= 400ms

In the third case, the devices chosen were 20-23 (Fig. 16). These devices had different threshold voltages and G_fs. We had the worst case with an imbalanced current of 50A.

During this test, some devices failed due to the high temperature. In this analysis, the key parameter was the threshold voltage V_th. Summarized in the chart (Fig. 17) are all tests done on the devices and the difference in current imbalance vs. the V_p between two devices. The chart shows that to obtain a current imbalance <5A, we have to choose a max different of 0.02V of V_p. Therefore, we suggest that devices used in linear should be sorted by threshold voltages.

CONCLUSION

The use of power MOSFETs in parallel is necessary in applications that manage high power loads because the total current can be shared between many devices and maintain a uniform working temperature. A good device paralleling can be obtained if the following conditions are satisfied:

• Devices with similar parameters

• Asymmetric driving (different turning on and of driving)

• Symmetrical board layout

• Good thermal coupling by same heat sink

• Low parasitic oscillations

Those conditions are not easy to achieve but are strongly recommended if devices are used in parallel. Sorting by threshold voltage and G_fs makes it possible to reduce current imbalance.

Click here for the illustrations:

Figure 1, Figure 2, Figure 3, Figure 4, Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10, Figure 11, Figure 12, Figure 13, Figure 14, Figure 15, Figure 16, Figure 17