Taiwan Semiconductor Manufacturing Co. Ltd (TSMC) has released an enhanced version of its 0.13-micron process to benefit customers' cost and competition and to enable the integration of power management functions. The 0.13-micron/0.11-micron family now includes a slim standard cell, SRAM and I/O with substantial area reduction and the 0.13-micron process also adopts LD-MOS (5V~20V) on RF platforms to enable analog and power management applications. The slim platform is available in the third quarter this year while the LD-MOS on RF platforms will be available in Q4 this year.
To meet the ever shrinking requirements for basic consumer and RF applications, the slim platform I/O area achieves a 30 percent reduction and SRAM bit cells demonstrate a 25 percent reduction when compared with traditional offerings. Furthermore, a 0.13-micron LD-MOS device built upon a RF platform enables SOC designs with power management functionality.
TSMC's investment in R&D for technology and IP portfolios within the 0.13-micron/0.11-micron family now delivers a true 5V with copper interconnect for the integration of analog, high-speed DSP, power management and watt-scale class-D amplification. Along with new features development for system-on-chip design, TSMC also offers a shrunken path to enhance customer's competitiveness including sub-node and slim technology platform. |
