Like most steps in the IC design flow, custom layout is becoming more tedious, complex and time consuming. To keep up with increasing die size, tight time-to-market requirements and new process-induced layout constraints, automation of the design process must constantly increase. Schematic-driven layout (SDL) is an automated capability that assists designers with the custom physical implementation of circuits (both analog and digital). SDL provides significantly faster layout by automatically maintaining continuity between logic and layout. SDL relies on device generation technology to automate the creation of physical layout from schematic elements.
The inflexibility of typical device generation technology has made SDL increasingly complex and difficult to use, and less productive for more complex analog and custom digital IC design. More advanced device generation technology takes SDL beyond mere drag-and-drop device generation by enabling a much more flexible, automated and controllable SDL flow. Its availability in a layout automation system provides designers a more efficient and effective way to create optimized layouts that don’t compromise layout density or design style.
SDL EVOLUTION
Through the years, the custom IC design process evolved from tedious creation of hand-drawn circuits to use of polygon layout editors that use cell models (devices or groups of devices) and hierarchical design to manage ever-increasing amounts of data. Schematic editors followed, allowing designers to draw circuit designs graphically on workstations. But communicating design intent from the circuit designer to the layout designer remained difficult, and required laborious review of the schematic and detailed, manual transfer of device attributes to layout. Layout vs. schematic (LVS) and design rule check (DRC) computer programs were introduced to catch connectivity/wiring errors (LVS) and manufacturing rule violations (DRC).
SDL, which allows engineers to automatically create a physical layout from a logic schematic, provided the next big leap in productivity. In a SDL flow, users select components in the schematic and “drag” them into the layout editor, which then automatically creates the physical design.
Analog and custom digital IC designers create schematics using symbols that correspond to specific devices. They assign values for a variety of parameters prior to layout based on the results of simulations run using foundry provided models. In the case of custom layout design, flexible configurations are required to create designs with optimal performance and the densest possible layout. Consequently, designers typically require a large variety of device sizes, meaning that hundreds or even thousands of different versions of each device would be required to create a useful and automated SDL flow.
SDL methodologies address the need for different device versions by using parameterized cells (PCells). PCells are software scripts (sequences of commands) that define physical layout based on a prescribed set of parameters. A single PCell takes the place of many fixed cells by allowing the substitution of different values for specified dimensional variables or parameters. The scripts, written primarily in proprietary formats (although they can also be written using an industry-standard format like Tcl), describe what the layout tool should do when an instance of the cell is used in the design, while the parameters quantify the values of the variables specified in the scripts to define the dimensions of that instance.
When PCells are placed using a SDL methodology, layouts are automatically generated that reflect the parameters and connectivity specified by the circuit designers in the schematic without having to enter any additional information or assign connectivity, thereby saving an enormous amount of time.
While SDL and PCells are a valuable combination, designers using conventional SDL flows are forced to consider the tradeoff between the time and effort required to set up and use PCells (their setup time requires writing scripts and establishing flows) and the ultimate goal of achieving faster layout results. Many layout designers end up using familiar manual methods rather than trust a complicated automated system to provide the necessary results. What today’s analog and custom digital IC designers require is a method that controls not only how often and how much automation is applied, but allows them control of the process. This methodology should be simple and intuitive to implement and enable layout results that rival the best manual layout without sacrificing design style or quality of results.
CONTROLLABLE AUTOMATION AND ADVANCED DEVICE GENERATION
Custom IC design does not lend itself well to the kind of automation currently available in automated place-and-route flows used in digital design. What custom IC designers need is controllable automation that enhances their expertise while removing tedious and non-productive actions from their workflow. The next evolution in SDL methodologies promises to address this need for controllable automation in the SDL flow, while enabling faster layout results with less effort. Specifically, it eliminates the need for time-consuming PCell scripting for the most common PCells.
At the heart of this evolution is a device generation technology that provides a more flexible and dynamic way of generating an optimized device layout (Figure 1). It utilizes parameterized devices that can be used in a similar manner as PCells with all the associated benefits. However, these devices are independent of the foundry, process or technology being used. The devices are categorized according to type (for example, resistors, capacitors, transistors, guard rings, and contacts/vias) and are readable as layout data in GDSII by EDA tools.
While utilizing a more automated device generation approach to enhance an SDL flow is very attractive, it also enables a more automated and fully controllable SDL flow. Control comes from intuitive, user-friendly device planning, wiring and manipulation capabilities.
One such capability is symbolic device optimization. It helps users optimize the device floorplan at a symbolic level without having to worry about parameters, design rules or connectivity (Figure 2). Once the floorplanning is complete and the design has been optimized for things like area, routing or even the shape of the available space, the device layout is automatically generated to match the floorplan. The layout retains the connectivity and sizing defined in the schematic.
This same technology can be applied to resistor and capacitor layout, and to accelerate even more complex layout problems like that of matching devices (Figure 3). Matching device layout can benefit significantly from a controllable SDL flow where the key layout planning issues can be addressed at a symbolic level and design-rule correct layout generated automatically. This capability is extremely valuable for analog devices, which are especially sensitive to process variation and circuit noise, and require special layout techniques to minimize the effects of process variability required to “match” devices.
For efficient layout of repeated circuitry patterns, a pattern duplication capability adds even more automation to the SDL flow. It helps group multiple circuit elements together that form repeating patterns, generate layout for that grouping, automatically locate identical patterns throughout the design, and then reuse the layout throughout the circuit (Figure 4). This capability dramatically speeds layout of repeated patterns.
For even more compact layout, repeated patterns can be optimized using a technique called pattern reuse. It works the same way as pattern duplication except that the repeated circuit pattern can be flattened and full-custom layout performed using the described SDL flow. This method combines all of the benefits of full custom layout using SDL with the speed of pattern duplication. Using pattern reuse, the flattened pattern maintains complete connectivity and cross-probing capability without affecting the schematic view itself.
Schematic-driven layout offers many benefits for today’s analog and custom digital IC designers, but automation without control oftentimes forces designers to face undesirable tradeoffs between setup time and layout speed. Flexible device generation technology provides a way to overcome this challenge by enabling controllable automation in an advanced SDL flow. Not only does it place more control of the automation in the hands of the designer, it also enables a range of capabilities which designers can use to realize a superior layout result with substantially less time and effort. With circuit designs continuing to get bigger and more complex, such capabilities will be critical to ensuring the analog and custom digital ICs of today and tomorrow get their designs to market on time and ahead of the competition.
About the author
Rich Morse is a Technical Marketing and EDA Alliances Manager for the Laker Custom IC Design products at SpringSoft.
Click here for the illustrations: Figure 1, Figure 2, Figure 3, Figure 4 |
