Design filters efficiently using simulation tool

Designing filters efficiently and accurately can be a challenge even when sophisticated simulation tools are available. It is difficult to obtain accurate circuit simulations due to closed-loop formulas that represent the components in a design. The challenge is to design circuits accurately to minimize or eliminate post-production tuning and reduce design iteration cycles, saving both time and development cost. Electromagnetic simulation, which is now more or less an integral part of any commercial RF/microwave simulation software, can help designers meet this challenge.



This article compares two band-pass filter (BPF) examples that were simulated using circuit and EM simulators. The simulation procedure is based on Agilent's advanced design system (ADS) EDA software, but it is applicable to any software with circuit and EM simulation capabilities.



To save time and effort, the initial filter was designed using the passive circuit guide available in ADS, at center frequencies of 4,500 and 5,350MHz, with bandwidth of 225MHz. The circuit was optimized to fine-tune filter performance and achieve desired results. The circuit design was then transferred to layout for electromagnetic simulation (using momentum).



Guidelines

Both the filters were designed on 25mil alumina substrate with a 1” x 1” fabricated circuit, relativedielectric constant (Er) of 9.9, and

loss tangent (tan ) of 7 10-4. The number of cells per wavelength for EM analysis was kept at 25, and the edge mesh option was selected because the first and the last coupled sections were spaced at 2.5mil (as shown in Figure 2). The edge mesh feature creates a relatively dense mesh pattern of small cells along the edges of metal. This is because most of the current flow occurs along the edges of slots or metals, and a denser edge mesh gives better solution accuracy.

The most important part of EM simulation is the mesh setup. Using the wavelength of the frequency, a linear function is approximated, also referred to as a rooftop basis function. The higher the frequency, the more wavelengths fit across the structure. More cells mean better sinusoid that is represented and the more accurate the simulation. For example, if 30 cells per wavelength are used, the maximum deviation between the sinusoid and the linear approximation is about 1 percent. These parameters affect longitudinal current.











Higher frequencies will result in an increased density for a mesh. Similarly, increasing the minimum number of cells per wavelength will also increase the density. In general, it is better to increase the number of cells per wavelength rather than increase the mesh frequency. This avoids having to recalculate the substrate frequency band if it is not sufficient.



The cell size used when the geometry is infinitely large corresponds with the number of cells per wavelength. But when other details, edges and user-defined mesh settings are included, cells may appear smaller than λ/20, resulting to more cells per wavelength than the value that was entered. There are two specific cases where the actual number of cells per wavelength is greater:



1. When the layout has details that are smaller than λ/20, the mesh follows the shape of the details. Since the mesh consists of triangles and rectangles only, the cells will be less than λ/20.



2. When the default settings in the dialog box are changed, it directly influences the number of cells over the width of the transmission lines. This may lead to cells that are smaller than λ/20.





Edge mesh

Amicrostrip transmission line with a bend, using the default mesh, may have a cell size equal to the width of the line (one cell per linewidth). If it is long and the bend is not severe, the default mesh may be adequate because the discontinuity is proportionally small compared to the line-length. However, if the reference planes are moved inward or if the bend is more severe, the discontinuity and resulting parasitics are in greater proportion to the rest of the line. The default mesh may result in simulation inaccuracies.



To correct inaccuracies, the mesh should be increased and edge mesh should be used. When the area near the discontinuity is meshed so that the cell size is equal to a three cells per line-width, the resulting error is reduced. The denser mesh allows for current crowding (parasitic series inductance) at the interior corner of the bend and charge build-up (parasitic shunt capacitance) at the outer edge of the bend.



The edge mesh feature automatically creates a relatively dense mesh pattern of small cells along the edges of metal or slots, and a less dense mesh pattern of a few large cells in all other areas of the geometry. Because most of the current flow occurs along the edges of slots or metals, the edge mesh provides an efficient solution with greater accuracy.





Transmission line mesh

Use the edge mesh to improve simulation accuracy when solving circuits where current flow modeling is critical. This includes circuits where the characteristic impedance or propagation constant are critical in determining the electrical model, circuits in which close proximity coupling occurs, or circuits where edge currents dominate the circuit behavior. Applications for using the edge mesh include tightly coupled lines, patch antennas, resonant circuits, delay lines and hairpin filters.



Use the transmission line mesh when the number of cells between parallel lines in a layout needs to be specified. This feature can save computation time and memory because it will create a mesh that is appropriate for straight-line geometry. For example, the simulation results for a single transmission line with one or two cells across the width will be equal. If the circuit has coupled lines, the results will differ.



















Simulated and measured results for BPFs are shown in Figures 3, 4, 5 and 6. EM simulation provides results that are quite close to the measured results. Circuit performance can be predicted using EM simulation, helping to reduce the post-production tuning problems often faced by designers reducing design cycle time.