Lead frames lead the way

With explosive growth continuing in the RF/wireless, portable applications, consumer and PC peripheral markets (PDA, camcorders, cameras, digital music), the demand for high performance and increased I/O counts in a smaller package has never been more intense. Advances in lead frame packaging, including quad flat no lead (QFN) and enhanced leadless lead frame-based packages such as the etched leadless package (ELP) using wire bond, SIP and flip chip technologies have continued to evolve to meet these customer needs.



The good news is that new enhancements such as multi-row array formats, flip chip, stacked die and SiPs, which are made to existing QFN-style packages, are using standard material sets and an existing infrastructure already in place. This provides a perfect landscape for an industry that continues to push for lower cost performance packaging in an ever shrinking form factor.



LOOKING AT ENHANCED LEADLESS PACKAGES

Multi row QFN lead frame packages Let’s take a look at multi-row QFN packaging or enhanced leadless packages. These packages offer benefits of a greater I/O density, design flexibility and improved electrical performance.



ELP has a multi-row capability whereby the cost advantage per I/O will be significant over QFN and two-layer laminate package options. In fact, ELP packages can be configured with multiple rows of lead frame posts and power/ground ring options along with the ability to isolate signal pads, and enable I/O signal routing that standard QFNs cannot offer (Figure 1).







These design features provide increased design flexibility and greater I/O density over the standard QFN package. Additionally, ELP solutions use standard industry material sets that don’t require a new infrastructure. There is no metal cutting which provides many benefits such as higher cut speeds, no smearing or burrs and no package chipping. This enables a robust singulation process with a longer saw blade life, increased units per hour (UPH) and better yields. An efficient robust assembly process coupled with the ability to strip test ensures that this becomes a cost effective package.



Lastly, the ELP package allows for a shorter path from chip to board for better thermal and electrical performance. The die is directly attached to an exposed metal DAP for improved thermal performance. Similar to the QFN, the ELP allows for wire bonding directly to a lead frame post. After the etch process, the post is a short direct path to the mating printed circuit board (PCB). In addition, the ELP can be configured to have rings to provide short wire bond options to power and ground signals.





Flip chip lead frame packages

Both ELP and ELGA flip chip packages improve performance by eliminating the wire bonds and providing a direct signal path from the bump to the lead frame post and then on to the mating PCB. This makes them more reliable since packages can achieve higher MSL ratings. Additionally, flip chip lead frames have improved thermal and electrical performance when compared to wire bond versions.



Lower inductance, resistance and higher capacitance values can be achieved as well as shorter time delay for high speed applications. And then there’s the real estate advantage. You can put more I/Os in a given die size which makes it possible to shrink the die giving more dice per wafer and finally cost reduction on wafers.





Stacked die lead frame packages

Let’s take a look at stacked dies. By stacking die, package functionality is added without increasing the package footprint. Functionality is added by package efficiency in Z direction. Single device packages can be combined to free up space on a PCB board.



According to TechSearch International a typical stacking configuration includes two die (memory and logic) in one package with a number of packages increasing the stacking to three or four devices.



Future stack die packages will contain more than four devices. However, this involves design and assembly related challenges that include signal to lead compatibility and die stacking assembly issues such as wafer thinning/preparation, die attach capability/control, epoxy bleed, outgassing, low loop requirement with high consistency and wire bonding on overhang die, etc.



Assembly equipment and material advancements such as special die attach material such as die attach film (DAF) and epoxy Assembly equipment and material advancements such as special die attach material such as die attach film (DAF) and epoxy with spacers are also being deployed to improve bond line control. New mold compounds compatible to the internal configuration must be considered to ensure high reliability. An upgrade in the assembly equipment such as wire bond

machines and die attach are required as well to handle the current assembly challenges as well as future technology demands (Figure 2).









SiP lead frame packages

The QFN system-in-package (SiP) technology is emerging as a reliable and lower-cost alternative to substrate based MCMs and SOC designs. In addition, SiP solutions provide superior flexibility, enabling wireless manufacturers to more easily support multiple standards, modes, and technologies (Figure 3).







As the complexity of circuit functionality grows, so does the number of IC elements. IC design challenges are magnified if the product must be integrated into a wide variety of applications. It is nearly impossible to put all of this functionality on one IC. As a result, package assemblers must take ICs and passives from multiple suppliers and then design and assemble all of this circuitry on the motherboard to support the required functionality. By implementing SIP technology, the complexity is transferred to the SiP package instead of the wireless device mother board.



By far, the major benefit of SiP technology is the integrated functionality provided by adding the support circuitry to the SiP package. Most OEMs are downsizing their manufacturing operations as a way to save costs, and demanding that their component suppliers provide a more value-added product. They are turning to packaging subcontractors as a valued resource for addressing the myriad of technical challenges associated with SiP technology.



By outsourcing the assembly of the SiP, OEMs can now specify a single integrated component instead of a discrete active device plus multiple passives. This integration can be implemented across multiple platforms, giving the OEM the benefit of economies of scale that translate directly into lower pricing. By using subcontractors to perform assembly tasks, the normal overhead associated with the SIP manufacturing is moved to a lower-cost operating center and, since the subcontractor builds for multiple customers, the OEM is only charged for its portion of the lines.



As the OEM’s volumes undergo inevitable seasonal or market-driven variations, there is no longer a non-revenue generating overhead burden, thus bolstering the bottom line during bad economic times.





CONCLUSION

Clearly, new enhanced leadless packages demonstrate how lead frame solutions are positioned for the future. Manufactures looking for ways to cut production costs should clearly look at the evolving advantages of the latest lead frame packaging. Leadless and enhanced leadless packages offer increase I/O counts and design flexibility, improved electrical and thermal performance and superior pack-age reliability. Taking advantage of an existing infrastructure and utilizing standard material sets, leadless packages are a very attractive alternative for many applications such as cellular phones and the portable consumer markets (PDA, camcorders, cameras, digital music) as cost and performance continue to drive package choice in an industry that continues to shrink die sizes and package footprint requirements.